A 50 to 70 GHz Power Amplifier Using 90 nm CMOS Technology

A 50 to 70 GHz wideband power amplifier (PA) is developed in MS/RF 90 nm 1P9M CMOS process. This PA achieves a measured P_sat of 13.8 dBm, P_{1 dB} of 10.3 dBm, power added efficiency (PAE) of 12.6%, and linear power gain of 30 dB at 60 GHz under V_DD biased at 1.8 V. When V_DD is biased at 3 V, it exhibits P_sat of 18 dBm, P_{1 dB} of 12 dBm, PAE of 15%, and linear gain of 32.4 dB at 60 GHz. The MMIC PA also has a wide 3 dB bandwidth from 50 to 70 GHz, with a chip size of 0.66 times 0.5 mm². To the author's knowledge, this PA demonstrates the highest output power, with the highest gain among the reported CMOS PAs in V-band.     

A 20 to 24 GHz $+$16.8 dBm Fully Integrated Power Amplifier Using 0.18 $mu{rm m}$ CMOS Process

A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm², which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm², which is the smallest one compared to all reported paper.     

High power-added efficiency MMIC amplifier for 2.4 GHz wirelesscommunications

This work describes the design and the measured performance of a high-efficiency monolithic microwave integrated circuit (MMIC) amplifier for wireless communications in the 2.4 GHz band. The monolithic technology employed in the circuit integration is based on standard 0.5-μm-gate-length MESFET. The design procedure is based on load-cycle graphic optimization of the transistor performance. On-wafer experimental characterization shows output power up to 24 dBm and excellent results of power-added efficiency up to 79% with 19.5 dBm output power at low drain bias voltage. The amplifier performance achieved and the circuit size, which is 1 mm², are suitable for use in the transmitter chains of wireless communication systems in the 2.4 GHz band     

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

A 5-10 GHz octave-band AlGaAs/GaAs HBT-Schottky diodedown-converter MMIC

The authors describe an AlGaAs/GaAs heterojunction bipolar transistor (HBT) X-band down-converter monolithic microwave integrated circuit (MMIC) which integrates a double double-balanced Schottky mixer and five stages of HBT amplification to achieve greater than 30 dB conversion gain over an RF bandwidth from 5 to 10 GHz. In addition, an output IP3 as high as +15 dBm has been achieved. The Schottky diodes are constructed from the existing N^$collector and N⁺ subcollector layers of the HBT molecular beam epitaxy (MBE) device structure. A novel HBT amplifier topology employing active feedback which provides wide bandwidth in a compact area is used for the RF, LO, and IF amplifier stages. The complete down-converter MMIC is realized in a 3.6×3.4 mm² area, is self-biased through a 6 V supply, and consumes 530 mW. This MMIC represents the highest complexity X-band down-converter MMIC demonstrated using GaAs HBT-Schottky diode technology     

A unique MMIC broadband power amplifier approach

A broadband monolithic microwave integrated circuit (MMIC) power amplifier design approach is described using lossy matching networks in the form of a bridged-T all-pass network. This approach offers the advantage of exceptional gain flatness, good input VSWR, high efficiency, and small size. A two-stage amplifier is described that delivers power greater than 1 W across the 2 to 6-GHz range with a linear gain of 20 dB, an input VSWR better than 1.7:1, and a power-added efficiency of 30% to 37% with a chip area less than 4.4 mm²     

A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control

A + 20 dBm power amplifier (PA) for applications in the 60 GHz industrial scientific medical (ISM) band is presented. The PA is fabricated in a 0.13-mum SiGe BiCMOS process technology and features a fully-integrated on-chip RMS power detector for automatic level control (ALC), built-in self test and voltage standing wave ratio (VSWR) protection. The single-stage push-pull amplifier uses center-tapped microstrips for a highly efficient and compact layout with a core area of 0.075 mm². The PA can deliver up to 20 dBm, which to date, is the highest reported output power at mm-wave frequencies in silicon without the need for power combining. At 60 GHz it achieves a peak power gain of 18 dB, a 1-dB compression (P1dB) of 13.1 dBm, and a peak power-added efficiency (PAE) of 12.7%. The amplifier is programmable through a three-wire serial digital interface enabeling an adaptive bias control from a 4-V supply.     

GaAs HBT wideband matrix distributed and Darlington feedbackamplifiers to 24 GHz

The designs and performances of a 2-24 GHz distributed matrix amplifier and 1-20 GHz 2-stage Darlington coupled amplifier based on an advanced HBT MBE profile that increases the bandwidth response of the distributed and Darlington amplifiers by providing lower base-emitter and collector-base capacitances are presented. The matrix amplifier has a 9.5 dB nominal gain and a 3-dB bandwidth to 24 GHz. This result benchmarks the highest bandwidth reported for an HBT distributed amplifier. The input and output VSWRs are less than 1.5:1 and 2.0:1, respectively. The total power consumed is less than 60 mW. The chip size measures 2.5×2.6 mm². The 2-stage Darlington amplifier has 7 dB gain and 3-dB bandwidth beyond 20 GHz. The input and output VSWRs are less than 1.5:1 and 2.3:1, respectively. This amplifier consumes 380 mW of power and has a chip size of 1.66×1.05 mm²      

A GaAs upconverter MMIC with an automatic gain control amplifierfor 1.9 GHz PHS

A newly developed GaAs upconverter MMIC with an automatic gain control (AGC) amplifier is presented. The design objectives, considerations, problems, and their solutions are described. The circuit is designed for a 1.9 GHz radio-frequency transceiver for the Japanese Personal Handyphone System applications. The features of the upconverter are: (1) on-chip 50 Ω impedance matching for all AC input and output signals; (2) a doubly balanced Gilbert cell and a two-stage AGC amplifier with matching circuits that provide 23.0 dB conversion gain, -39 dBc LO suppression, -23 dBc image suppression, and 30 dB gain control; (3) an adjacent channel power of -70 dBc, and (4) a die size of only 2.87 mm² (2.52 mm×1.14 mm)     

1.6 W hybrid master oscillator power amplifier withα-DFB-laser as master oscillator at 1057 nm

A hybrid master oscillator power amplifier is realised on a small area less than 100 mm² combining an α-DFB-laser as master oscillator and a broad area laser as power amplifier. A quasi-cw output power of P=1.6 W at the wavelength) λ=1057 nm is achieved with a beam quality factor M² less than 2 and a spectral width less than 6 pm     

A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $mu$m SiGe BiCMOS Technology

This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm². The chip was measured in packaged prototypes using 48-pin ceramic LCC packages.     

A 9.1–10.7 GHz 10-W, 40-dB Gain Four-Stage PHEMT MMIC Power Amplifier

This letter presents a compact X-band high gain and high power four-stage AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) high power amplifier (PA). This amplifier is designed to fully match a 50-Omega input and output impedance. Based on 0.35-mum gate-length power PHEMT technology, this PA MMIC is fabricated on a 3-mil thick wafer. While operating under 8 V and 2700-mA dc bias condition, the characteristics of 40-dB small-signal gain, a 10-W continuous-wave saturation output power, and 33% power added efficiency at 9.7GHz can be achieved     

A DC-11.5 GHz Low-Power, Wideband Amplifier Using Splitting-Load Inductive Peaking Technique

A DC-11.5 GHz low-power amplifier is developed in commercial 0.13 mum, CMOS technology. This amplifier design is based on a three-stage shunt-feedback inverter-configuration with splitting load inductive peaking technique. The peaking inductor is placed at the gate of the nMOS to compensate gain roll-off of the inverter stage and extend its operating bandwidth. This amplifier achieves a gain flatness of 13.21 dB from dc to 11.5 GHz with I/O return losses better than 17 dB at a power consumption of 9.1 mW. The measured noise figure is less than 5.6 dB between 1-11 GHz. The output P1 dB is 8 dBm and input third-order intercept point is 10 dBm. The total chip size is 0.34 mm² including all testing pads, with a core area of only 0.08 mm².     

Large bandwidth BiCMOS operational amplifiers for SC videoapplications

A single-ended and a fully differential broadband BiCMOS operational amplifier for switched-capacitor video applications are presented. The amplifiers feature a folded cascode gain stage with a current source as output load. For the single-ended amplifier the current mirroring is accomplished with a modified bipolar Wilson current mirror at the output of the differential pair. Symbolic expressions for the transfer functions for both amplifiers are derived. The amplifiers are integrated in an analog 1 μm BiCMOS process with an active die area of 0.72 mm² and 0.96 mm² for the single-ended and the fully differential amplifier, respectively. For both amplifiers a DC-gain of 68 dB and a unity gain frequency greater than 250 MHz was measured for a power supply voltage of 5 V     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback

This paper presents an inductorless circuit technique for CMOS limiting amplifiers. By employing the third-order interleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18-mum CMOS process, the limiting amplifier is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a -3-dB bandwidth of 9 GHz. With a 2³¹-1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10^-12 are 300 and 10 mV_pp, respectively. Due to the absence of the spiral inductors, the chip size of the limiting amplifier including the pads is 0.68times0.8 mm² where the active circuit area only occupies 0.32times0.6 mm²     

A 77-GHz MMIC power amplifier for automotive radar applications

A MMIC 77-GHz two-stage power amplifier (PA) is reported in this letter. This MMIC chip demonstrated a measured small signal gain of over 10 dB from 75 GHz to 80 GHz with 18.5-dBm output power at 1 dB compression. The maximum small signal gain is above 12 dB from 77 to 78 GHz. The saturated output power is better than 21.5 dBm and the maximum power added efficiency is 10% between 75 GHz and 78 GHz. This chip is fabricated using 0.1-/spl mu/m AlGaAs/InGaAs/GaAs PHEMT MMIC process on 4-mil GaAs substrate. The output power performance is the highest among the reported 4-mil MMIC GaAs HEMT PAs at this frequency and therefore it is suitable for the 77-GHz automotive radar systems and related transmitter applications in W-band.     

A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier

A monolithic SiGe BiCMOS envelope-tracking power amplifier (PA) is demonstrated for 802.11g OFDM applications at 2.4 GHz. The 4-mm² die includes a high-efficiency high-precision envelope amplifier and a two-stage SiGe HBT PA for RF amplification. Off-chip digital predistortion is employed to improve EVM performance. The two-stage amplifier exhibits 12-dB gain, <5% EVM, 20-dBm OFDM output power, and an overall efficiency (including the envelope amplifier) of 28%.     

Monolithic 10 GHz TDR/TDT analyser with novel architecture

A simple and low-cost time-domain reflectometer using two pulse generators and a high bandwidth sample and hold amplifier is presented. The design has been achieved using an MMIC commercial foundry process from OMMIC (pHEMT f_t=100 GHz). The bandwidth of the sampler is more than 10 GHz and the minimum pulse width generated is less than 50 ps. The total active area is less than 3 mm²     

A small chip size 2 W, 62% efficient HBT MMIC for 3 V PCNapplications

This work describes the L-band low voltage (⩾1.6 V) power performance of AlGAs/GaAs heterojunction bipolar transistors (HBTs), their modeling and the design of a 2-W monolithic microwave integrated circuit (MMIC) for 3-V wireless mobile PCN applications (1800 MHz). The two-stage MMIC achieves 62% power-added efficiency (PAE) and 33 dB of linear gain, at a very small chip size of 1.2 mm². To our knowledge this is the best combination of power performance data for wireless applications demonstrated so far for a MMIC. The chip size is about a factor of four smaller than comparable MMIC's known before. The MMIC offers the potential both for low cost production due to small chip size, single voltage supply, and high performance at the same time