A 14-ns 1-Mbit CMOS SRAM with variable bit organization

The authors describe a 14-ns 1-Mb CMOS SRAM (static random-access memory) with both 1M word×1-b and 256 K word×4-b organizations. The desired organization is selected by forcing the state of an external pin. The fast access time is achieved by the use of a shorter divided-word-line (DWL) structure, a highly sensitive sense amplifier, a gate-controlled data-bus driver, and a dual-level precharging technique. The 0.7-μm double-aluminum and triple-polysilicon process technology with trench isolation offers a memory cell size of 41.6 μm² and a chip size of 86.6 mm ². The variable bit-organization function reduces the testing time while keeping the measurement accuracy of the access times     

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.     

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.     

A 1-Mbit CMOS EPROM with enhanced verification

A high-speed 1-Mb EPROM (erasable programmable read-only memory) with an enhanced verify mode to insure adequate threshold shift after programming has been developed. The sense circuitry uses an offset current to shift the sense point to require higher threshold shift during verification. The access time is improved by a clocking scheme that balances the sensing circuitry between column accesses and by a chip architecture optimized for speed. The chip features an access time of 70 ns and an active current of 20 mA. A typical programming time of 50 μs has been measured. The device is processed in a 1-μm L _eff CMOS process with silicides     

A reliable 1-Mbit DRAM with a multi-bit-test mode

A single 50V supply 1-Mb DRAM using a half V/SUB cc/ biased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal is described. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide world-line technology.     

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Powering billions of devices is one of the most challenging barrier in achieving the future vision of IoT. Most of the sensor nodes for IoT based systems depend on battery as their power source and therefore fail to meet the design goals of lifetime power supply, cost, reliable sensing and transmission. Energy harvesting has the potential to supplant batteries and thus prevents frequent battery replacement. However, energy autonomous systems suffer from sudden power variations due to change in external natural sources and results in loss of data. The memory system is a main component which can improve or decrease performance dramatically. The latest versions of many computing system use chip multiprocessor (CMP) with on-chip cache memory organized as array of SRAM cell. In this paper, we outline the challenges involved with the efficient power supply causing power outage in energy autonomous/self-powered systems. Also, various techniques both at circuit level and system level are discussed which ensures reliable operation of IoT device during power failure. We review the emerging non-volatile memories and explore the possibility of integrating STT-MTJ as prospective candidate for low power solution to energy harvesting based IoT applications. An ultra-low power hybrid NV-SRAM cell is designed by integrating MTJ in the conventional 6T SRAM cell. The proposed LP8T2MTJ NV-SRAM cell is then analyzed using multiple key performance parameters including read/write energies, backup/restore energies, access times and noise margins. The proposed LP8T2MTJ cell is compared to conventional 6T SRAM counterpart indicating similar read and write performance. Also, comparison with the existing MTJ based NV-SRAM cells show 51–78% reduction in backup energy and 42–70% reduction in restore energy.     

A 1-Mbit CMOS dynamic RAM with design-for test functions

A 1-Mb CMOS DRAM measuring 4.3/spl times/11.7 mm/SUP 2/ (50.32 mm/SUP 2/) has been fabricated using 1.0-/spl mu/m CMOS double-poly single-metal process technology. Both moat and second-level poly are clad to reduce circuit propagation delays. The chip incorporates two modes of 8-bit parallel READ/WRITE, as well as additional functions for test-time reduction. Eight 1-Mb family members can be produced by metal mask selection. The device uses static column circuitry along with two-stage intermediate output buffers to achieve a typical column address access time of 20 ns.     

A 6-F/sup 2/ bit cell design based on one transistor and two uneven magnetic tunnel junctions structure and low power design for MRAM

Novel cell structures based on one transistor and two uneven magnetic tunnel junction cell and pillar write word line architecture are proposed to shrink the bit size with a potential down to 6 F/sup 2/ by a so-called extended via process, and to reduce the writing current by a factor of 2, combined with the nature of nonvolatility and high speed, making the magnetoresistive random access memory suitable for universal memory applications.     

基于体积分方程的三维集成电路互连线电磁快速求解器

三维集成电路通过高密度金属互连线实现芯片在三维空间上互连,其电路参数的快速提取是保证信号完整性良好设计的关键技术之一.文中基于体积分混合势积分方程（mixed potential integral equation,MPIE）方法,结合多层平面介质格林函数与预纠正快速傅里叶变换（pre-corrected fast fourier transformation,pFFT）方法,通过对互连线内趋肤电流准确建模,实现对互连线结构S参数的快速准确提取.通过对典型互连线结构的仿真表明,本文求解器得到的结果与商业软件HFSS结果在网格剖分考虑趋肤效应时,其精度相当,计算效率可提高50%以上.所以本文方法在三维集成电路互连线参数快速提取方面具有一定的应用前景.     

A vertically integrated dynamic RAM-cell: Buried bit line memory cell with floating transfer layer

A charge injection device has been realized in which charge can be injected on to an MOS-capacitor from a buried layer via an isolated transfer layer. The cell is positioned vertically between word and bit line. LOCOS (local oxidation) is used to isolate the cells and (deep) ion implantation to realize the buried bit line and transfer layer. This isolation prevents carriers from diffusing to neighbouring cells and hence preserves stored information. The device physics has been analysed using simulation programs and bipolar modelling. It is shown that this device can be used as a dynamic RAM-cell of extreme simplicity and potentially small cell size compared to conventional DRAM cells.     

A 70-ns word-wide 1-Mbit ROM with on-chip error-correction circuits

A 1-Mb ROM has been developed, organized as either 64K/spl times/16 or 128K/spl times/8 in a pin-selectable option. Multiplexing the address inputs and the data outputs onto the same pins makes it possible to fit into a 28-pin package and to perform straightforward interfacing with some popular 16-bit microprocessors. The process technology is a 1.5-/spl mu/m twin-well double-level-metal CMOS on a grounded p-type substrate. The device uses some dynamic circuitry during the start of the active cycle, but automatically takes itself back into the static precharge state-except for the latched outputs. Typical access time is 70 ns. New high-speed error detection and correction circuits were developed which work in about 10 ns. Because all 16 outputs are not driven at once, but half are delayed by about 15 ns through a process-tracking delay circuit, the on-chip error correction is finished before the process-tracking delay circuit is through, and error correction costs no further access penalty. These error correction circuits enhance both yield and reliability.     

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.<>     

A 0.24-/spl mu/m 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme

A nonvolatile 16-kb one-transistor one-magnetic-tunnel-junction (1T1MTJ) magnetoresistance random access memory with 0.24-/spl mu/m design rules was developed by using a self-reference sensing scheme for reliable sensing margin. This self-reference sensing scheme was achieved by first storing a voltage of the magnetic tunnel junction (MTJ), and then after a time interval storing a reference voltage of the same MTJ (self-reference). The effects of variation in tunneling oxide thickness can be eliminated by this self-reference sensing scheme. As a result, reliable sensing of MRAM devices with MTJ resistance of 2.5-11 k/spl Omega/ was achieved.     

A 1-Mbit CMOS dynamic RAM with a divided bitline matrix architecture

A 1-Mb dynamic RAM has been fabricated using 1.2-/spl mu/m double-level metal CMOS technology. A novel divided bitline matrix architecture allows the conventional double-polysilicon planar memory cell to be used without sacrificing signal-to-noise (S/N) ratio or die efficiency. Optimized for high bandwidth, the device uses static column circuitry and a 256K/spl times/4 organization to achieve data rates >180 Mb/s at worst-case voltage and temperature conditions. The 5.97-mm/spl times/11.4-mm die incorporates a flexible laser blown fuse link redundancy scheme which can repair a wide variety of fabrication defects. Typical row access and cycle times are 85 and 190 ns, respectively, achieving >21-Mb/s bandwidth in the non-optimized row access mode. Although some DC power is dissipated in static circuitry, active power consumption has been kept to 225 mW (45 mA), and standby power consumption has been reduced to 2.5 mW (0.5 mA).     

A 4-Mbit DRAM with folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell

A 5-V 4-Mb word/spl times/1-b/1-Mb word/spl times/4-b dynamic RAM with a static column model and fast page mode has been built in a 0.8-/spl mu/m twin-tub CMOS technology with single-metal, two-polycide, and single poly-Si interconnections. It uses an innovative folded-bit-line adaptive sidewall-isolated capacitor (FASIC) cell that measures 10.9 /spl mu/m/SUP 2/ and requires only a 2-/spl mu/m trench to obtain a storage capacitor of 50 fF with 10-nm SiO/SUB 2/ equivalent dielectric film. A shared-PMOS sense-amplifier architecture used in this DRAM provides a low power consumption, small C/SUB B/-to-C/SUB S/ capacitance ratio, and accurate reference level for the nonboosted word-line scheme with little area penalty. These concepts have allowed the DRAM to be housed in the industry standard 300-mil dual-in-line package with performances of 90-ns RAS access time and 30-ns column address access time.     

A 1-Mbit DRAM with 33-MHz serial I/O ports

High-speed operation, a 33-MHz serial cycle, and a 10-ns serial data access time have been realized by internal serial/parallel conversion circuits, a newly designed I/O controller circuit, new dynamic register circuits, a divided sensing method, and an optimized layout design. The chip is fabricated with a 1.2-/spl mu/m double-level polysilicon and double-level aluminium n-channel MOS process technology. An optimized interlevel insulator realizes equivalent first- and second-level aluminium pitches for a compact chip design. The chip size is 5.88/spl times/11.2 mm/SUP 2/. This memory has high-speed input and output capability as well as random accessibility. These features are suitable for TV and VCR frame-memory-system applications.     

A redundancy test-time reduction technique in 1-Mbit DRAM with amultibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M×1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test     

A 1-Mbit CMOS DRAM with fast page mode and static column mode

A 1-Mb words/spl times/1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology is described. More than 2.2 million devices are integrated on a 62.5 mm/SUP 2/ silicon chip by utilizing an n-channel memory cell of triple-level poly Si structure and a 1.2-/spl mu/m feature size VLSI process. Novel CMOS circuit design techniques such as the half V/SUB cc/ bitline precharge scheme are successfully applied to realize the excellent performance combination of high-speed operation and low-power dissipation. The CMOS peripheral circuitry is capable of the new operating functions, fast page mode, or static column mode with metal mask options. The typical RAS access time is 56 ns, the active current is 30 mA at a 190-ns cycle time, and the standby current is 0.2 mA.     

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable referencebit-line voltage scheme using a fatigue-free reference capacitor

A 0.5-μm, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance C_ferr is larger than reference-cell capacitance C_MOS. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme     

基于1 bit时间调制技术的功率控制方法

针对传统数控衰减器结构复杂、控制信号路数多的问题,提出了一种基于1 bit时间调制技术的功率控制方法. 通过对1 bit移相器0°和180°两种状态占空比的调节,该方法可以有效实现对输入信号基波功率的动态控制,利用带通滤波器抑制多余谐波后其可具备数控衰减器的功能. 还进一步讨论了调制信号时间精度对不同衰减量和不同调制频率的约束. 仿真和实验结果验证了所提功率控制方法的有效性. 相比于传统数字控制衰减器级联网络和多路控制信号的结构,本文方法只需一个调制模块和两路控制信号即可实现多种衰减状态可调的功能,因此具备结构简单的优势.