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1.
将相邻线间的信号跳变方向考虑到噪声窗口模型中,提高计算同时跳变的干扰线在受扰线上引起的组合噪声脉冲结果的准确性;利用改进的噪声窗口模型,对受扰线的弱干扰线集合、强干扰线集合以及传播噪声同时进行分析,得到电路中精确的可实现有效噪声脉冲以及相应的有效干扰线集合。对10个MCNC基准电路进行实验,结果表明,该方法能够非常有效地滤除功能噪声分析过程中的虚假噪声故障。  相似文献   

2.
To solve the crosstalk noise problem in deep-submicron technologies, a statistical method for analyzing crosstalk noise with reduced distributed RC-π model is proposed in this paper. First, quiet aggressor net and tree branch reduction techniques are introduced into the distributed RC-π model, and a new spatial correlation model for both Gaussian and non-Gaussian process variations among segments is created. Then, principal components analysis (PCA) and independent component analysis (ICA) techniques are applied to reduce correlations of process variations. Finally, the moment matching scheme is used to obtain the probability density function (PDF) of crosstalk noise in victim coupled with multiple aggressors. Experimental results show that our method maintains the efficiency of previous approaches, and significantly improves on their accuracy.  相似文献   

3.
针对高速数字电路PCB中传输线间串扰的严重性,从精确分析PCB中串扰噪声的角度出发,在传统的双线耦合模型的基础上,采用了一种三线串扰耦合模型。该模型由两条攻击线和一条受害线组成,两条攻击线位于受害线的两侧,线间采取平行耦合的方式。利用信号完整性仿真软件Hyperlynx对受害线上的近端串扰噪声和远端串扰噪声进行了仿真。仿真结果表明,不同的传输模式和传输线类型、信号层与地平面的距离、耦合长度、传输线间距和信号上升/下降沿等因素会对受害线上的近端串扰和远端串扰产生较大的影响。在分析仿真结果的基础上,总结出了高速PCB设计中抑制串扰的有效措施,对高速数字电路设计有一定的指导意义。  相似文献   

4.
As CMOS technology continues to scale down, circuits become increasingly more sensitive to transient pulses caused by single event (SE) particles. On the other hand, coupling effects among interconnects can cause single event transients to contaminate electronically unrelated circuit paths which may increase the SE susceptibility of CMOS circuits. The coupling effects among interconnects need to be considered in single event hardening, modeling and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. This work, for the first time, proposes an SE crosstalk noise estimation method for use in design automation tools. The proposed method uses an accurate 4-π model for interconnect and correctly models the effect of non-switching aggressors as well as aggressor tree branches noting the resistive shielding effect. The SE crosstalk noise expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is about 5.2% while allowing for very fast analysis in comparison to HSPICE.  相似文献   

5.
In this paper, the most relevant characteristics of the substrate noise spectrum for mixed-signal integrated circuits (ICs) are derived using a simple analytical model. These characteristics are related to parameters of the digital circuit, the package + printed circuit board parasitics, and other elements of the mixed-signal IC. The model used to derive the substrate noise spectral characteristics includes the statistical properties of the digital switching current waveform and the coupling transfer function between the digital power supply nodes and the substrate node of the victim circuitry. The results of the work are validated experimentally on a mixed-signal prototype.  相似文献   

6.
7.
Shows the results of studies of noise induced by various combinations of parasitic capacitances and inductances. Interconnects are simulated with parameters obtained from a 0.18 /spl mu/m process. The four kinds of noise addressed are (i) crosstalk pulse; (ii) crosstalk speedup and slowdown; (iii) oscillatory noise; (iv) combination of oscillatory noise and crosstalk pulse. The crosstalk effects induced by a combination of mutual capacitance and mutual inductance can be larger than those induced by mutual capacitance alone, even if capacitive crosstalk dominates. For certain interconnects that are capacitively and inductively coupled, transitions in the same direction on an aggressor and victim line can cause speedup or slowdown, depending on timing parameters. A similar observation holds for transitions in opposite directions. We also observe that oscillatory noise can combine with crosstalk pulse under certain skew conditions and give rise to a large magnitude of noise. We show that inductance induced noise can be a problem in medium length interconnects. Because such interconnects can occur in combinational logic blocks, the generation of suitable vectors for test and validation of such logic blocks is of concern.  相似文献   

8.
A self-consistent one-dimensional large-signal analysis of a Read-type IMPATT diode oscillator has been developed which takes into account the device-circuit interaction. The circuit is modeled by a lumped-equivalent network representing the diode package, and a cascade of lossless transmission lines with discontinuity capacitances representing the coaxial-line cavity with tuning slugs. A particular voltage waveform across the semiconductor wafer is not assumed a priori. Instead, the voltage and current waveforms are determined iteratively until they satisfy the equations for both the diode model and for the circuit. The waveforms are found to be highly dependent upon the circuit in which the diode is embedded.  相似文献   

9.
This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation.  相似文献   

10.
Using behavioral models to perform fast simulation is currently a popular solution to verify SOC designs. Previous analog behavior modeling approaches often treat the noisy ${rm V}_{rm DD}$ waveform as a given input and focus on reflecting such stimuli on circuit performance. However, because the interaction of noise aggressors and victims is not considered, some error may exist while compared with real simulation results. In this paper, a simple SCORE macromodel is proposed for PLL designs to help noise-aware behavioral models handle supply noise interaction effects. The time-varying supply noise waveform and real-time PLL responses can be obtained simultaneously with accurate noise estimations in this recursive approach. As demonstrated in the experimental results, the proposed approach can provide more realistic results with noise interaction effects but still keep fast simulation time.   相似文献   

11.
This article focusses on the waveform analysis and crosstalk peak estimation at far-end of victim line for simultaneously switching inputs with resistive drivers. A low loss coupled transmission line-model of interconnect is used for analytical purpose. Noise peaks are estimated for the conditions when inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analysed in general with homogeneous and non-homogeneous drivers for unipolar inputs. The driver is modelled as linear resistance. Comparison of the analytical results with simulation programme with integrated circuit emphasis (SPICE)-extracted results shows that the error involved is less than 2% and 5% for in-phase and out-of-phase switching, respectively. The comparisons of analytically obtained results with SPICE simulations show that the proposed model captures noise peaks, their timings and waveform shape for all switching conditions with an average error of less than 4%.  相似文献   

12.
For the first time, compact physical models are derived for crosstalk noise of coplanar resistance-inductance-capacitance lines in a gigascale integration (GSI) chip that simultaneously consider far and near aggressors in both the same metal level and distant metal levels. Since both the amplitude and duration of noise are important, the noise voltage-time integral can be defined as a figure-of-merit for crosstalk, and it is shown that this integral attains its maximum at the length at which the interconnect resistance becomes equal to twice the characteristic impedance. It is also shown that crosstalk can be prohibitively large if interconnects have small resistances. There is, therefore, a tradeoff between interconnect latency and crosstalk. The compact models are finally used to calculate the crosstalk noise voltage for the case that wire width is optimized by simultaneously maximizing data flux density and minimizing latency. It has been proven that by utilizing the optimal wire width for signal interconnects and twice of that for power and ground lines, the worst case peak crosstalk noise voltage becomes smaller than 0.25 V/sub dd/ for all generations of technology.  相似文献   

13.
采用电磁范数对系统电磁脉冲(SGEMP)脉冲电流注入(PCI)波形参数的确定方法进行研究。负载分别为高阻和低阻时,对SGEMP敏感端口响应典型波形进行电磁范数参数化表征,综合考虑等效波形的上升时间、峰值、携带的能量和电荷量与响应波形的差异情况,开展了PCI等效波形参数研究。仿真结果表明,方波等效波形可以很好地模拟出响应波形,等效波形与响应波形的峰值一致,频谱特征近似;等效波形的上升时间、携带的能量和电荷量等参数通过调整脉宽即可实现与响应波形一致。因此,可采用电磁范数对SGEMP响应波形进行参数化表征等效,获得的等效波形容易在实验室生成,从而为采用电流注入方法开展SGEMP研究提供一种新的途径。  相似文献   

14.
Frequency noise and modulation of a four-section DBR laser   总被引:1,自引:0,他引:1  
A theoretical model is presented to describe the tuning, frequency noise, and modulation characteristics of tunable DBR lasers with two active and two passive sections. Analytical expressions are derived for the intensity and frequency modulation responses, frequency noise spectrum, spectral linewidth, effective linewidth enhancement factor, and spontaneous emission rate. It is shown that a nearly flat red-shifted FM response over several gigahertz can be obtained by nonuniform current injection and modulation of the lower carrier density section in the active region. Increasing the tuning current through the passive sections enhances the FM efficiency. However, a higher FM efficiency is generally accompanied by a larger spectral linewidth. The predictions of our theoretical model are in good agreement with the available experimental data  相似文献   

15.
16.
Three-dimensional (3D) integration is a key technology for systems whose performance and power requirements cannot be achieved by traditional silicon technologies. 3D chips consist of two or more stacked silicon dies connected by short inter-die wires called Thru-Silicon-Vias (TSVs). Despite its potential, the poor reliability and yield, thermal management and testing issues remain major challenges of 3D integration. We address the TSV interconnect test challenge of 3D chips by using Interconnect Built-In Self-Test (IBIST) techniques. The proposed test strategy must sensitize structural faults like opens and shorts, and delay faults due to crosstalk. A possible approach is the well-known Maximum Aggressor Fault (MAF) model. Unfortunately, this model is too conservative and it leads to long test sequences and non-negligible hardware costs. Therefore, we present an alternative solution: the Kth-Aggressor Fault (KAF) model. In our model, aggressors of victim wires are neighboring wires within an optimized distance order K. The aggressor order K is technology-dependent and is determined such that the test times are minimal and the fault coverage is maximal. KAF-based IBIST implementation targeting TSV tests occupies three times less area than similar MAF-/marching-based implementations. We also propose a reconfigurable KAF-based IBIST implementation where tests can be performed using different aggressor orders K. Although the reconfigurable IBIST area is significant, interconnect tests during system lifetime can be performed using lower aggressor orders, reducing test duration and improving TSV availability.  相似文献   

17.
A time-domain noise model is developed for analyzing the performance degradation of wireless communication systems in the 2.4 GHz band caused by microwave ovens, taking into account the noise generation mechanism and its characteristics. The proposed noise model consists of a series of frequency-modulated tone bursts, which can be realized with a set of FM/AM modulators. It yields a simple and general expression of the noise waveform in terms of six parameters that can be determined from measurements. Band-limited noise waveforms can also be derived from the model via simple approximations. Comparisons of both the waveform and the frequency spectrum are made between actual noise and the proposed model, which clearly demonstrate the validity and usefulness of the model.  相似文献   

18.
Timing jitter (phase noise) and power fluctuations (intensity noise) in a semiconductor laser driven with a periodic current waveform, in the large signal regime are investigated theoretically. The temporal behavior of the laser output power is calculated numerically from the modified rate equation with Monte Carlo simulation of the random processes, both free-running and active mode-locked configurations are treated. The temporal width and root-mean-square (rms) timing jitter and energy fluctuation of the pulses are calculated, as are the correlation and spectral properties of the noise  相似文献   

19.
This paper describes a rigorous and systematic procedure to derive a unified and complete semidistributed FET model that can be easily implemented in CAD routines of simulators. We have used the three coupled-line theory, including active and passive electromagnetic coupling between the semiconductor electrodes. The analytical formulas are given in order to calculate the capacitances of the electrodes and sufficient agreement is obtained in comparison with numerical analysis. For the first time, the experimental data of the device are compared with full three coupled-line theory and three coupled-line sliced model. This full semidistributed approach to FET modeling is applied to the analysis of a submicrometer-gate GaAs FET at centimeter and millimeter-wave frequencies, and the results are compared with the lumped element approach. The maximum available power gain (MAG) and the maximum stable power gain (MSG) of the device are calculated as a function of device width and frequency. Both the losses caused by the channel and those caused by the finite electrode conductivity are included. Good agreement is obtained between theory and experiment  相似文献   

20.
Long-wavelength semiconductor laser amplifiers are investigated with respect to spectral gain properties such as peak gain wavelength shift and width of gain curve, employing different structural parameters such as thickness of the active layer and amplifier length. The model takes into account Auger recombination, thermal effects, and spontaneous emission. It is shown that there exists an optimum thickness of the active layer with respect to current density for a given gain and that increased length of the amplifier allows higher gains and reduced variation of peak gain wavelength with respect to variation of peak gain at the expense of increased saturation by amplified spontaneous emission and increased excess noise. An experimental verification of the theoretical model is reported  相似文献   

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