Reindustrialization: A telecommunications perspective

There is a convergence of opinion that there is need for the United States to reindustrialize. But there is a divergence of opinion concerning how such reindustrialization should be accomplished. This article examines the concept of reindustrialization, with particular emphasis upon telecommunications and institutional frameworks.     

DSP嵌入式系统人机接口设计

介绍利用DSP2812作为嵌入式控制器的人机交互界面实例以及SED1335液晶控制器和PS/2键盘在实际应用中的处理方法.并对RT320240B液晶屏的刷新速度和PS/2键盘的误码情况进行分析.针对DSP驱动大尺寸液晶屏显示刷新速率较慢,提出利用外部接口总线并行控制的改进方案,大幅提高液晶刷新速度.该接口设计主要应用于具有板级BIST功能的数据采集系统中,并可广泛适用于各种嵌入式系统,实现灵活,实用价值高.     

一种支持高效加法的FPGA嵌入式DSP IP设计

提出了一种支持可变位宽高效加法的现场可编程逻辑门阵列(FPGA)嵌入式数字信号处理(DSP)单元知识产权(IP)硬核结构,相比于Altera公司的Stratix-III DSP结构,基于本文提出的优化结构可以更高效地实现加法、乘加以及累加等多种应用。利用软件对不同数据类型和位宽的输入实现数据预处理,减小了硬件资源的开销,并进一步提升了电路性能。同时在DSP结构中加入了乘法旁路器和二级符号位扩展的加法电路,在减小DSP实现面积的同时,支持超高位宽、高速的流水线型加法运算,扩展了DSP的应用范围。采用TSMC 55 nm标准CMOS工艺设计并完成了所提出的DSP IP核的电路实现,可实现包括72位可变位宽加法及36位可变位宽乘法等在内的9种运算模式。     

A historical perspective on telecommunications networksynchronization

Network synchronization, at first unknown and considered irrelevant to the operation and performance of telecommunications networks, has played an increasingly important role throughout the evolution of telecommunications, especially since transmission and switching became digital. This survey deals with telecommunications network synchronization from a historical point of view, aiming to show how network synchronization issues have evolved with telephone networks over the last 30 years, beginning with old FDM networks up to the latest technologies through PDH, SDH/SONET, and ATM. For each case, the different synchronization needs and the peculiar techniques of timing transfer and distribution are pointed out, thus providing a comprehensive overview of the evolution steps of telecommunications network synchronization     

A Sigma-Delta ADC design automation tool with embedded performance estimator

A system-level design automation tool for designing discrete time, switched-capacitor, Sigma-Delta analog-to-digital converters is presented. The presented work utilizes a performance estimator based on EKV models. The design automation tool takes advantage of high level analytical single-bit and multibit models of the building blocks. With the contribution of the performance estimator module, the tool provides an extensive design environment for designing Sigma-Delta analog-to-digital converters. Developed models and their effects are presented with examples. Design examples for 0.5 and technologies are provided for proving the flexibility of the design automation tool.     

A systems approach for national telecommunications policy

It is argued that the arrival of the age of information networking in the US is being slowed by the patchwork of ground rules in the telecommunications industry, which prevents the open and universal provision of information networking and related services, and that a national policy is needed. The history of regulatory policy is reviewed, and the current situation is described. The importance of user needs and wants in setting policy is described, and the use of a systems approach is suggested     

Distributed systems for telecommunications

The authors present an overview of the January/February 1994 issue of IEEE Network which includes seven articles on distributed telecommunications systems     

A trade perspective of international telecommunications issues

This article illustrates how the principles and tools of trade policy provide a framework for dealing with trade-distortive actions while ensuring a stable and predictable environment in which trade and technological innovation can prosper. It describes why communication has become a trade issue, what trade policy is all about, and some typical trade problems in telecommunications. The article concludes with a discussion of possibilities of longer-term rule-making efforts in international telecommunications.     

A communication theory perspective on telecommunications policy

The relationship of emerging telecommunications networks to our social situation, especially in terms of technical, economic, and legal arrangements, has not yet been fully defined or decided. James Carey (1989) established a fundamental distinction between two models of communication that is important for understanding sociocultural implications of contemporary telecommunications policy. In this essay, these contrasting models are used to illuminate historical tensions between the policy goals of liberalization and democratization. Current telecommunications policy discourse, drawing upon a transmission framework, aims to achieve liberalization of telecommunications markets. It also invites us to ignore questions of power in the context of democratization, which the community, cultural, and ritual aspects of Carey's model explicitly demand we address.     

Energy-efficient design of battery-powered embedded systems

Energy-efficient design of battery-powered systems demands optimizations in both hardware and software. We present a modular approach for enhancing instruction level simulators with cycle-accurate simulation of energy dissipation in embedded systems. Our methodology has tightly coupled component models thus making our approach more accurate. Performance and energy computed by our simulator are within a 5% tolerance of hardware measurements on the SmartBadge. We show how the simulation methodology can be used for hardware design exploration aimed at enhancing the SmartBadge with real-time MPEG video feature. In addition, we present a profiler that relates energy consumption to the source code. Using the profiler we can quickly and easily redesign the MP3 audio decoder software to run in real time on the SmartBadge with low energy consumption. Performance increase of 92% and energy consumption decrease of 77% over the original executable specification have been achieved     

面向工业电脑与嵌入式系统的节电长效内存

自动化和控制技术、计量、机器人以及安全领域的工业应用对所用内存组件及模块的要求与标准PC或办公应用有所不同。多数情况下，这些领域的重点并不是基于最新工艺技术的终极性能，而是最高的可靠性、紧凑性、质量和低功耗，同时还有较长的产品周期和相关的供货保证。     

A general time model for the specification and design of embedded real-time systems

Design of complex embedded systems feasible with current and upcoming semiconductor technologies necessitates consideration of real-time from the beginning. However, the commonly used specification techniques do not consider temporal aspects in general like fulfillment of high level timing requirements or dynamic reactions on timing violations. In this paper, we discuss the restrictions of current specification techniques for embedded real-time systems and present a general time model that solves this issue. The time model contains the progress of time, the measurement of time and the specification of timing requirements based on event traces. In contrast to earlier techniques, preconditions determine the actual relevance of a specific timing bound. Exemplified for SDL, a solution for the specification of temporal aspects is shown. The advantages of this solution are discussed in a hardware/software co-design case study from the mobile communication area.     

Software engineering for telecommunications : bringing research results into industrial practice

As networks and services are becoming more and more sophisticated, telecommunications software is growing in complexity. But, despite growing industrial needs, progress towards more software productivity has been extremely slow. This paper considers the software engineering problems from an industrial point of view. The industrial environment is therefore presented in some detail, stressing the influence of major events (e.g. company mergers) on fundamental software development issues (e.g. configuration management). The evolution of this environment, caused by recent trends such as deregulation, is then described, forecasting the consequences for software development. Then some emerging software techniques are presented as applied (or applicable) to telecommunications software. The paper concludes with a discussion of several research issues that could be of interest for industry within a reasonable time-frame.     

Estimating and reducing the memory requirements of signal processing codes for embedded systems

Most embedded systems have limited amount of memory. In contrast, the memory requirements of the digital signal processing (DSP) and video processing codes (in nested loops, in particular) running on embedded systems is significant. This paper addresses the problem of estimating and reducing the amount of memory needed for transfers of data in embedded systems. First, the problem of estimating the region associated with a statement or the set of elements referenced by a statement during the execution of nested loops is analyzed. For a fixed execution ordering, a quantitative analysis of the number of elements referenced is presented; exact expressions for uniformly generated references and a close upper and lower bound for nonuniformly generated references are derived. Second, in addition to presenting an algorithm that computes the total memory required, this paper also discusses the effect of transformations (that change the execution ordering) on the lifetimes of array variables, i.e., the time between the first and last accesses to a given array location. The term maximum window size is introduced, and quantitative expressions are derived to compute the maximum window size. A detailed analysis of the effect of unimodular transformations on data locality, including the calculation of the maximum window size, is presented.     

DSP应用系统的电源设计

本文主要介绍了TI公司TMS320C6000系列芯片的供电系统设计。整个系统采用单5V电源供电,用高效率的同步电压转换芯片提供稳定的DSP内核电压(1.9V)和周边I/O接口电压(3.3V),同时巧妙地解决了两种供电的顺序问题,并增设了电源监控和复位电路,可以同时监测5V、3.3V和1.9V,确保供电系统稳定、高效地工作。     

An optimization based design for integrated dependable real-time embedded systems

Moving from the traditional federated design paradigm, integration of mixed-criticality software components onto common computing platforms is increasingly being adopted by automotive, avionics and the control industry. This method faces new challenges such as the integration of varied functionalities (dependability, responsiveness, power consumption, etc.) under platform resource constraints and the prevention of error propagation. Based on model driven architecture and platform based design’s principles, we present a systematic mapping process for such integration adhering a transformation based design methodology. Our aim is to convert/transform initial platform independent application specifications into post integration platform specific models. In this paper, a heuristic based resource allocation approach is depicted for the consolidated mapping of safety critical and non-safety critical applications onto a common computing platform meeting particularly dependability/fault-tolerance and real-time requirements. We develop a supporting tool suite for the proposed framework, where VIATRA (VIsual Automated model TRAnsformations) is used as a transformation tool at different design steps. We validate the process and provide experimental results to show the effectiveness, performance and robustness of the approach.     

Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog

Model Based System Engineering (MBSE) is a renowned approach in the context of embedded systems development. It is frequently used to deal with the structural and behavioral aspects of system design. However, the verification of system design is generally performed in isolation. It is particularly true in the context of assertion based verification. Consequently, there is a huge gap between system design and its verification that seriously effects the productivity and time-to market objectives. Therefore, in this research, we target to reduce this gap by exploiting the features of MBSE and SystemVerilog assertions (SVA’s). This article introduces a novel MBSE approach to model the design verification aspects of embedded systems, along with the system design (structural and behavioral aspects). We propose SystemVerilog in Object Constraint Language (SVOCL), an OCL temporal extension for SystemVerilog, to represent the design verification requirements by means of SVA’s. As a part of research, SVOCL transformation engine has been developed to generate SVA’s code in order to automate the design verification of embedded systems. The application of SVOCL has been validated through four case studies.