New resistorless tunable voltage-mode universal filter using single VDIBA

To increase the universality of the recently introduced voltage differencing inverting buffered amplifier (VDIBA), this letter presents a new voltage-mode (VM) multi-input–single-output (MISO) universal filter. The proposed filter contains only single VDIBA, two capacitors, and one nMOS transistor, operated in triode region, and is used for resonance angular frequency tuning. Since in the structure no resistors are needed the filter can be classified as resistorless. The VM MISO filter compared with other active building block-based counterparts is very simple, it contains only few transistors, and has the smallest size area. Moreover, no component matching is required and it shows low sensitivity performance. The theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 SCN018 CMOS process parameters with ±0.9 V supply voltages. In addition, the behavior of the proposed VM filter was also experimentally verified using commercially available integrated circuits OPA660 and AD830.     

New CMOS realization of high performance Voltage Differencing Inverting Buffered Amplifier and its filter application

This paper describes a high performance voltage differencing inverting buffered amplifier (VDIBA). The transconductance of the proposed circuit is enhanced by using positive feedback technique with only two extra transistors used in active load. Moreover, the bandwidth of proposed circuit is enhanced by using resistive compensation technique. The performance of proposed VDIBA is demonstrated by detailed frequency analysis. Furthermore, it is shown that the transconductance can be enhanced up to 4.61 mS at biasing current of 300 µA. In addition, a third order low pass filter is given as an application example to confirm the high performance of the proposed VDIBA. The proposed low pass filter operates at natural pole frequency of 15 MHz. The proposed VDIBA and its filter application are implemented using TSMC 90 nm CMOS technology in Cadence virtuoso schematic composer at ±0.6 V supply voltage.     

Design and Analysis of Tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) with Enhanced Performance and Its Application in Filters

This paper proposes a high performance tunable Voltage Differencing Inverting Buffered Amplifier (VDIBA) where transconductance of VDIBA is enhanced by using programmable positive feedback technique and bandwidth is enhanced by using resistive compensation technique. The enhanced performance of proposed VDIBA is demonstrated by presenting detailed frequency analysis. Furthermore, it is verified that transconductance of proposed VDIBA can be enhanced up to 10.6 mS at tuning current (Ic) of 100 µA. Moreover, resistive compensation technique enhance bandwidth of propose circuit up to 263 MHz. To illustrate the effectiveness of proposed circuit, voltage mode universal biquad filter is designed as an application example. The pole frequency of proposed filter is tunable in range of 10.5–83.4 MHz. The proposed VDIBA and its filter applications are designed and simulated using TSMC 0.18 µm CMOS technology in Cadence virtuoso schematic composer at ± 0.6 V supply voltage.     

Low-voltage low-power FGMOS based VDIBA and its application as universal filter

This paper presents Floating gate MOS (FGMOS) based low-voltage low-power variant of recently proposed active element namely Voltage Differencing Inverting Buffered Amplifier (VDIBA). The proposed configuration operates at lower supply voltage ±0.75 V with the total quiescent power consumption of 1.5 mW at the biasing current of 100 µA. Further the operating frequency of the proposed VDIBA is improved by using the resistive compensation method of bandwidth extension in Operational Transconductance Amplifier (OTA) stage of the block. By using resistive compensation method of bandwidth extension, the bandwidth of OTA stage increases from 92.47 MHz to 220.67 MHz. As an application, proposed FGMOS based VDIBA has been used to realize a novel resistorless voltage mode (VM) universal filter. The proposed universal filter configuration is capable of realizing all the standard filter functions in both inverting and non-inverting forms simultaneously without any matching constraint. Other important features include independently tunable filter parameters, cascadibility and low sensitivity figure. The proposed filter is tunable over the frequency range of 4.1 MHz to 12.9 MHz and is capable of compensating for process, voltage and temperature (PVT) variation. The simulations are performed using SPICE and TSMC 0.18 µm CMOS technology parameters with±0.75 V supply voltage to validate the effectiveness of the proposed circuit.     

Voltage-Mode New Universal Biquad Filter Configuration Using a Single VDIBA

A universal voltage-mode filter configuration employing a voltage differencing inverting buffered amplifier (VDIBA), two capacitors and a resistor is proposed. The presented structure can realize all the five standard biquadratic filters: low-pass, high-pass, band-pass, band-reject and all-pass, without changing the circuit topology. The proposed filter circuit also provides the following advantageous features, not available simultaneously in any of the single active element/device based universal biquad realizing all the five filter responses known earlier so far: (i) independent electronic tuning of natural angular frequency (ω ₀) and bandwidth (BW), (ii) no requirement of any element matching condition or inversion of input signal(s) (as needed in most of the earlier reported structures), and (iii) low active and passive sensitivities. Moreover, even the internal structure of the new building block is possibly the simplest among all recently introduced new building blocks. The workability of the proposed filter has been confirmed by SPICE simulations using 0.18 μm technology.     

Current mode first order universal filter and multiphase sinusoidal oscillator

In this article a new current mode first order universal filter with single input and multiple outputs is proposed. The realization uses single dual-X multiple output second generation current conveyor (DX-MOCCII) and two passive grounded components. The presented circuit provides high-pass, low-pass and non-inverting and inverting all-pass responses simultaneously, all at different high impedance outputs. The realized circuit does not require any component matching constraint and all the sensitivities are found low. As an application the non-inverting all-pass filter is cascaded in a close loop with the current mode non-inverting integrator to design a current mode multiphase sinusoidal oscillator (MSO) having six phases. Voltage mode six phase sinusoidal oscillator is also achieved by resistively loading the current mode outputs. The analysis such as phase noise, non-ideality, stability and Monte Carlo are presented and discussed. The presented theory and its results are validated using 0.25 µm process parameters of TSMC in PSPICE simulator.     

Three-Level Inverter-Based Shunt Active Power Filter in Three-Phase Three-Wire and Four-Wire Systems

This paper presents a direct current-space-vector control of an active power filter (APF) based on a three-level neutral-point-clamped (NPC) voltage-source inverter. The proposed method indirectly generates the compensation current reference by using an equivalent conductance of the fundamental component using APF's dc-link voltage control. The proposed control can selectively choose harmonic current components by real-time fast Fourier transform to generate the compensation current. The compensation current is represented in a rotating coordinate system with chosen switching states from a switching table implemented in a field-programmable gate array. In addition, a three-phase four-wire APF based on a three-level neutral-point-clamped inverter is also presented. The proposed APF eliminates harmonics in all three phases as well as the neutral current. A three-phase three-wire NPC inverter system can be used as a three-phase four-wire system since the split dc capacitors provide a neutral connection. To regulate and balance the split dc-capacitor voltages, a new control method using a sign cubical hysteresis controller is proposed. The characteristics of the APF system with an LCL-ripple filter are investigated and compared with traditional current control strategies to evaluate the inherent advantages. The simulation and experimental results validated the feasibility of the proposed APF.      

All digital fast lock DLL-based frequency multiplier

One of the most important parameters in the design of synthesizers is lock time. A new fast lock delay locked loop (DLL) based frequency multiplier is proposed in this paper. Phase detector, charge pump and loop filter in conventional DLLs are replaced by a digital signal processor in the proposed structure. This leads to have better lock time, higher speed and smaller chip aria. The proposed structure can be implemented easily in a real system by means of a suitable powerful digital signal processor. Simulation has been done for 11 delay cells as a delay chain and input frequency equal with 300 MHz. The output frequency is multiplied by 11 (f_OUT = 3.3 GHz), and lock time is obtained about 13 ns which is equal to 4 clock cycles of reference clock.     

Steady-State and Dynamic Study of Active Power Filter With Efficient FPGA-Based Control Algorithm

A new approach using field-programmable gate array (FPGA) to implement a fully digital control algorithm of active power filter (APF) is proposed in this paper. This FPGA-based controller integrates the whole signal-processing function of an APF, including synchronous-reference-frame transform, low-pass filter, three-phase phase-locked loop, inverter-current controller, etc. By case studies on the principle, performance, and architecture, these control blocks are implemented in real-time and synthesized into a medium-scale FPGA chip by adopting some useful digital-signal-processing techniques, such as pipelining, folding and strength reduction, with respect to minimization of hardware resource and enhancement of operating frequency. As a result, the whole algorithm needs around 5000 logic elements and can run at synchronous system-clock rates of up to 65 MHz. Experimental results on a laboratory prototype are given to demonstrate performance of the proposed approach during steady-state and dynamic operations.     

Novel CMOS realizations of the inverting second-generation current conveyor and applications

This paper presents two new CMOS realizations for the inverting current conveyor (ICCII). The proposed realizations offer enhanced features compared to previously reported ICCII. Also new oscillator circuits based on using the ICCII as an active element are presented. The presented oscillator circuits have the advantage that both the oscillation frequency and the oscillation condition can be adjusted independently. Also another application to the ICCII, which is a floating inductor, is proposed. A second order low pass filter using the proposed floating inductor is simulated and compared with the ideal result. The proposed ICCIIs and the presented applications are tested with SPICE simulations using CMOS 0.35 μm technology to verify the theoretical results.     

Synthesis of active inductors using SFG stamps

This paper proposes a new approach for the systematic synthesis of active inductors via signal-flow graphs (SFGs). The basic idea consists of proposing and using SFG stamps of active basic building blocks (ABBs) to construct the equivalent SFG of a classical inductor. We show that a large number of active inductors can be thus synthesized; twelve are proposed, most of them are novel. Known ABBs, as well as newly proposed ones are used, namely current conveyors (CC), operational transconductance amplifiers (OTA), current conveyor transconductance amplifiers (CCII-TA), current feedback operational amplifiers (CFOA), operational transresistance amplifiers (OTRA), current backward transconductance amplifiers (CBTA), current feedback transconductance amplifiers (CFTA) and voltage differencing inverting buffered amplifiers (VDIBA). SPICE simulations are given to show the viability of the proposed technique.     

Automatic Synthesis of VFs and VMs by Applying Genetic Algorithms

An automatic synthesis method is introduced to design voltage followers (VFs) and voltage mirrors (VMs) by performing evolutionary operations. It is shown that the nullor element is useful to introduce a new genetic representation to codify the behavior of the VF by a chromosome divided by four genes: small-signal (genSS), synthesis of the nullor by MOSFET (genSMos), bias (genBias), and synthesis of current mirrors (genCM). Further, it is shown that the behavior of the VM can be codified by evolving the chromosome of the VF. The proposed synthesis method uses SPICE to evaluate the fitness of the VF and VM. Finally, we show the synthesis of several VFs and VMs which are designed using standard CMOS technology of 0.35 μm. The applications and evolution of the VF and VM to synthesize more complex devices such as current conveyors (CCs) and inverting CCs are briefly discussed.     

A new fast settling low power CMOS gain stage architecture

This paper presents a new gain stage for high accuracy and fast settling applications. In the proposed structure a novel combination of closed loop and open loop amplifiers is employed to achieve high accuracy and enhanced settling behavior while adding only negligible power to the main circuit power constraint. To evaluate the functionality of the proposed idea, a zero cross based circuit and a switch capacitor amplifier are designed to implement the open loop and the closed loop stages, respectively. Though, other topologies for implementation of open loop and closed loop amplifiers are applicable in the presented gain stage. The proposed structure is implemented in 0.18 μm CMOS technology. HSPICE simulation results, using level 49 models, demonstrate that the new configuration improves the power efficiency and the settling behavior as well as the system accuracy. The proposed scheme shows very fast settling times of 0.8, 1.01, 1.41 ns for the gain accuracies of 6, 8 and 10 bits, respectively, while loaded with 1 pF capacitance and the output swing is 1.6 V. In comparison with a conventional switched capacitor closed loop amplifier, the proposed architecture improves the settling performance by a factor of 3 for 6 bit resolution, while it adds only 0.63 mW power to the total power consumption that is 8.68 mW.     

Design of a new low power MISO multi-mode universal biquad OTA-C filter

ABSTRACT

In this article, a new low-power multiple-input, single-output (MISO) multi-mode universal biquad operational transconductance amplifier-capacitor (OTA-C) filter with a minimum number of active and passive components is proposed. The proposed filter employs three OTAs, one inverter and two grounded capacitors. The proposed filter can realise all filter frequency responses including low-pass (LP), band-pass (BP), high-pass (HP), band-stop (BS) and all-pass (AP) in all operation modes including voltage, current, tranasresistance and transconductance modes using the same topology. Furthermore, sensitivity analysis is done which shows that the proposed filter has a low sensitivity to the values of the active and passive elements. The proposed filter is simulated in HSPICE using 0.18 µm CMOS technology. The HSPICE simulation results demonstrate that the proposed filter consumes only 35 μW at 2.5 MHz from a ±0.5 V supply voltage, while all of the transistors are biased in strong inversion region. Also, the simulation results are in a close agreement with the theoretical analysis which is done in MATLAB. Furthermore, the process, voltage and temperature variation simulations are done to study the effect of non-idealities on the performance of the proposed filter. It is shown that the simulation results justify a 4.8%, 0.8% and 20% variations of the centre frequency for process, voltage and temperature, respectively. Finally, Monte-Carlo, noise and transient simulations are done to justify the good performance of the proposed filter performance.     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

A new CMOS design of high transconductance current follower transconductance amplifier and its applications

In this work, a new CMOS implementation of high transconductance current follower transconductance amplifier (CFTA) is proposed. The proposed CFTA uses current starving technique along with an auxiliary unit (AU) to enhance transconductance performance. The cross-drain-coupled MOSFETs are also used in AU which further enhances transconductance of proposed circuit. The proposed CFTA provides higher transconductance and wider tuning range without affecting its output swing and bandwidth performance. The proposed CFTA provides transconductance of 11.3 mS, dissipates 1.8 mW power and operates at?±?0.6 V supply voltage. A current mode third order quadrature oscillator and biquad filter have been designed and simulated, to validate the performance of proposed circuit. The workability of proposed CFTA and its applications have been verified by using Cadence virtuoso schematic composer with TSMC 0.18 µm process parameters.     

Continuous-time delta-sigma modulator using vector filter in feedback path to reduce effect of clock jitter and excess loop delay

In this paper, we propose a novel delta-sigma modulator (DSM) that reduces the effects of clock jitter and excess loop delay by using a vector filter in the feedback path. The vector filter divides the input signal into a high-frequency part and a low-frequency part. The low-pass signal is placed in the path to the first-stage digital-to-analog converter for reducing the effects of the clock jitter, and the high-pass signal is placed in the feedback path to the last integrator in order to compensate for the excess loop delay. The DSM using the vector filter in the feedback path (DSM-VF) is verified using MATLAB/Simulink. Further, a clock jitter (0.1 %) in DSM-VF leads to an improvement in the signal-to-noise-ratio (SNR) to 22.5 dB as compared to the SNR of a conventional CTDSM. Moreover, the SNR deterioration caused by the excess loop delay is improved.     

A Cost-effective Sub-terahertz Continuous Wave Generation Scheme Using a Broadband Optical Source and An Optical Feedback Loop

We have proposed a cost-effective sub-terahertz (THz) continuous wave (CW) generation scheme based on a usual double sideband-suppressed carrier (DSB-SC) scheme. The usual DSB-SC scheme, which consists of a discrete optical source, an optical intensity modulator (OIM), a local oscillator (LO), an optical notch filter, and an erbium doped fiber amplifier (EDFA), is one of well-known photonic-based sub-THz CW generation schemes. As the discrete optical source of the usual DSB-SC scheme is eliminated and an optical feedback loop is incorporated with the usual DSB-SC scheme, our proposed scheme is constructed to decrease implementation costs. Without an optical input, the output of the pump laser of the DC-biased EDFA is inserted to the optical notch filter. Reflected lightwaves with fiber bragg grating wavelengths of the optical notch filter is fed back to the input of the OIM through the optical feedback loop, which is composed of a circulator and a 90:10-coupler. DSB-SC lightwaves have been made by modulating feedbacked lightwaves on the OIM with the frequency of the LO. A sub-THz CW is generated by photomixing them. To verify feasibility of our proposed scheme, we generated and characterized a 120 GHz CW. The measurement results were also compared to those of the usual DSB-SC scheme. Based on our measurement results, we found that characteristics of the generated 120 GHz CW using our proposed scheme are comparable to those using the usual DSB-SC scheme. Consequently, our proposed scheme can be helpful to make a cost-effective sub-THz CW generator based on photonics.     

A Modified CFOA and Its Applications to Simulated Inductors, Capacitance Multipliers, and Analog Filters

In this paper, using a minimum number of passive components, i.e., new grounded and floating inductance simulators, grounded capacitance multipliers, and frequency-dependent negative resistors (FDNRs) based on one/two modified current-feedback operational amplifiers (MCFOAs), are proposed. The type of the simulators depends on the passive element selection used in the structure of the circuit without requiring critical active and passive component-matching conditions and/or cancellation constraints. In order to show the flexibility of the proposed MCFOA, a single-input three-output (SITO) voltage-mode (VM) filter, two three-input single-output (TISO) VM filters, and an SITO current-mode (CM) filter employing a single MCFOA are reported. The layout of the proposed MCFOA is also given. A number of simulations using the SPICE program and some experimental tests are performed to exhibit the performance of the introduced structures.      

A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.