Effect of the post-gate annealing on the gate reliability of AlGaN/GaN HEMTs

In this paper,we investigated the effect of post-gate annealing (PGA) on reverse gate leakage and the reverse bias reli-ability of Al0.23Ga0.77N/GaN high electron mobility transistors (HEMTs).We found that the Poole-Frenkel (PF) emission is domin-ant in the reverse gate leakage current at the low reverse bias region (Vth ＜ VG ＜ 0 V) for the unannealed and annealed HEMTs.The emission barrier height of HEMT is increased from 0.139 to 0.256 eV after the PGA process,which results in a reduction of the reverse leakage current by more than one order.Besides,the reverse step stress was conducted to study the gate reliabil-ity of both HEMTs.After the stress,the unannealed HEMT shows a higher reverse leakage current due to the permanent dam-age of the Schottky gate.In contrast,the annealed HEMT shows a little change in reverse leakage current.This indicates that the PGA can reduce the reverse gate leakage and improve the gate reliability.     

Off-state breakdown effects on gate leakage current in powerpseudomorphic AlGaAs/InGaAs HEMTs

The effects of off-state breakdown on characteristics of power AlGaAs/InGaAs pseudomorphic HEMTs (PHEMTs) are investigated in detail. While the gate leakage current is substantially decreased after breakdown stress, no obvious changes in drain-to-source current and transconductance are observed. Prior to breakdown stress, gate leakage current shows a nearly ideal 1/f noise characteristic with an Ig² dependence, suggesting a surface generation-recombination current from the interface of the passivation layer. After stress, the gate current noise can be drastically reduced. The results suggest an alternative for alleviating the gate leakage current in PHEMTs     

Hot electron induced degradation of undoped AlGaN/GaN HFETs

This work presents the effects of hot electron stress on the degradation of undoped Al_0.3GaN_0.7/GaN power HFET’s with SiN passivation. Typical degradation characteristics consist of a decrease in the drain current and maximum transconductance, an increase in the drain series resistance, gate leakage and a subthreshold current. Degradation mechanism has been investigated by means of gate lag measurements (pulsed I-V) and current-mode deep level transient spectroscopy (DLTS). Stressed devices suffered from aggravated drain current slump (DC to RF dispersion) which indicates possible changes in surface charge profiles occurred during hot electron stress test. The DLTS was used to identify the trap creation by hot electron stress. The DLTS spectra of stressed device revealed the evidence of trap creation due to hot electron stress.     

Stability of short-channel P-channel polysilicon thin-filmtransistors with ECR N2O-plasma gate oxide

Stability of hydrogenated short-channel (⩽3 μm) p-channel poly-Si TFT's with very thin (12 nm) electron cyclotron resonance N₂O plasma gate oxide is investigated. The fabricated poly-Si TFT's with gate length not less than 2 μm show excellent stability characteristics of less than 0.1 V in the threshold voltage shift and less than 3% in the percent change of transconductance after harsh electrical stresses. In a small |V_G| stress, an effective shortening of channel length is observed due to trapping of hot-electrons and the minimum leakage current is decreased. However, a large |V_G| stress causes more degradation on the subthreshold slope and minimum leakage current due to trapping of hot-holes     

GaN-based HEMTs tested under high temperature storage test

In this work, the impact of 1000 h thermal storage test at 325 °C on the performance of gallium nitride high electron mobility transistors grown on Si substrates (GaN-on-Si HEMTs) is investigated. The extensive DC- and pulse-characterization performed before, during and after the stress did not reveal degradation on the channel conduction properties as well as formation of additional trapping states. The failure investigation has shown that only the gate and drain leakage currents were strongly affected by the high temperature storage test. The physical failure analysis revealed a Au inter-diffusion phenomenon with Ni at the gate level, resulting in a worsening of the gate–AlGaN interface. It is speculated that this phenomenon is at the origin of the gate and drain leakage current increasing.     

Generation mechanism of gate leakage current due to reverse-voltagestress in i-AlGaAs/n-GaAs HIGFETs

Device degradation characterized as an increase in the gate leakage current due to continuous reverse-voltage stress was investigated for a 0.35-μm WSi gate i-AlGaAs/n-GaAs doped channel HIGFET (heterostructure insulated-gate field-effect transistor). The gate leakage current, which was dominated by a hole current generated by impact ionization, was found to increase after the application of a gate-to-drain voltage of -6 V for a certain period. The occurrence of the impart ionization was evidenced by the generation of a substrate current and by the negative temperature coefficient of the gate current. The degradation was retarded at an elevated temperature, indicative of hot-carrier-related degradation. The degraded device also showed an ohmic-like gate leakage current. Subsequent annealing at temperatures above 300°C significantly restored the current-voltage (I-V) characteristics. From these observations, a degradation model was developed in which hot holes generated by impact ionization are trapped in the insulator/semiconductor interface, contracting the surface depletion region and thereby increasing the electric field near the gate-edge. A surface treatment using CF₄ plasma was used to suppress the degradation. An FET fabricated using this treatment showed a remarkable decrease in degradation     

Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses

The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this.     

Identification of stress-induced leakage current components and thecorresponding trap models in SiO2 films [MOStransistors]

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components     

Identification of stress-induced leakage current components and thecorresponding trap models in SiO2 films

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the-current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components     

Hot electrons induced degradation in lattice-matched InAlN/GaN high electron mobility transistors

In this paper, lattice-matched Pt/Au-In_0.17Al_0.83N/GaN high electron mobility transistors (HEMTs) were fabricated, and the degradation characteristics of the gate leakage current were investigated by drain-to-source voltage (V_DS) step-stress measurements under the ON, semi-ON, and OFF stress conditions and at different temperatures, respectively. It is found that, (1) there exists a critical value of V_DS, beyond which the gate leakage current begins to increase significantly; and (2) the degradation of gate leakage current has a positive temperature coefficient, indicating that high temperature can accelerate the degradation. A hot electron model is used to explain the experimental results, emphasizing that the hot electrons from the channel can induce additional negatively charged defects at the InAlN/GaN interface, which can increase the local electrical field and introduce a thinner surface barrier and finally enhance the vertical leakage current component, leading to the current degradation.     

高温及关态应力条件下GaAs pHEMT器件的性能退化研究

研究了高温和电学应力下砷化镓赝晶高电子迁移率晶体管的直流特性退化机理。高温下陷阱辅助发射电流引起器件关态漏电上升,而载流子迁移率的退化引起跨导降低;当温度达到450 K时,栅金属的沉降效应会导致跨导异常升高。进一步研究了不同温度下关态电学应力对器件性能退化的影响,结果与高温下栅沉降效应相吻合。     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

HfO_2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在 p- Si(1 0 0 )衬底上制备了 Hf O2 栅介质层 ,研究了 Hf O2 高 k栅介质的电流传输机制和应力引起泄漏电流 (SIL C)效应 .对 Hf O2 栅介质泄漏电流输运机制的分析表明 ,在电子由衬底注入的情况下 ,泄漏电流主要由 Schottky发射机制引起 ,而在电子由栅注入的情况下 ,泄漏电流由 Schottky发射和 Frenkel-Poole发射两种机制共同引起 .通过对 SIL C的分析 ,在没有加应力前 Hf O2 / Si界面层存在较少的界面陷阱 ,而加上负的栅压应力后在界面处会产生新的界面陷阱 ,随着新产生界面陷阱的增多 ,这时在衬底注入的情况下 ,电流传     

基于氟等离子体表面处理技术的AlGaN/GaN HEMT器件栅正向泄漏电流研究

The gate forward leakage current in AlGaN/GaN high electron mobility transistors(HEMTs) is investigated. It is shown that the current which originated from the forward biased Schottky-gate contributed to the gate forward leakage current.Therefore,a fluorine-plasma surface treatment is presented to induce the negative ions into the AlGaN layer which results in a higher metal-semiconductor barrier.Consequently,the gate forward leakage current shrinks.Experimental results confirm that the gate forward leakage current is decreased by one order magnitude lower than that of HEMT device without plasma treatment.In addition,the DC characteristics of the HEMT device with plasma treatment have been studied.     

Comparison of interfaces states density through their energy distribution and LVSILC induced by uniform and localized injections in 2.3 nm thick oxides

Experiments were performed on 2.3 nm thin gate oxides. The interface state density and the low voltage stress induced leakage current are compared after uniform and localized stresses. The energy distribution of interface state density in the bandgap is then determined. The normalized variations of interface state density and gate leakage current are shown to be comparable after localized stress but completely different after uniform stresses.     

F等离子体处理 AlGaN/GaN HEMT击穿电压和电流崩塌研究

F等离子体处理工艺被广泛的应用于 AlGaN/GaN HEMT增强型器件的研制和栅前处理工艺。本文研究了低功率F处理 AlGaN/GaN HEMT的击穿特性和电流崩塌特性。随着F处理时间的增加,饱和电流下降,阈值电压正向移动。对不同F处理时间的器件肖特基特性分析后发现,120s的F处理后器件栅泄漏电流明显减小,器件击穿电压提高,当F处理时间大于120s后,由于长时间F处理带来的损伤器件栅泄漏电流没有继续减小。采用不同偏置下的双脉冲测试对不同F处理时间的电流崩塌特性进行了研究,低功率F处理后没有发现明显的电流崩塌现象。     

PMOS breakdown effects on digital circuits – Modeling and analysis

The degradations in the pMOS device due to gate oxide breakdown introduced by voltage stress were investigated experimentally. The stress-induced shifts in gate leakage and I–V characteristics were presented. A combined Verilog-A and sub-circuit model was first time introduced and employed to simulate the pMOS breakdown behaviors. The Verilog-A model can accurately simulate the power law characteristics of breakdown gate leakage current with a fractional coefficient. With the developed model, the simulated results and the measurements have good agreements. The traditional logic circuits, such as the inverter and the latch, have been investigated through Cadence simulations with the improved models. The latch suffers from the gate oxide breakdown significantly. The NULL Convention Logic (NCL) circuit has also been examined and analyzed systematically. The results showed substitute degradations due to the pMOS gate oxide breakdown.     

总剂量辐照对65 nm NMOSFET热载流子敏感参数的影响

为了研究总剂量辐射对纳米MOS晶体管热载流子效应的影响,对65 nm 体硅工艺的NMOS器件进行了总剂量辐射和热载流子试验,对比了辐射前后不同宽长比器件的跨导、栅极泄漏电流、线性饱和电流等电参数。结果表明,MOS器件的沟道宽度越窄,热载流子效应受辐射的影响越显著,总剂量辐射后热载流子效应对器件的损伤增强。分析认为,辐射在STI中引入的陷阱电荷是导致以上现象的主要原因。该研究结果为辐射环境下器件的可靠性评估提供了依据。     

On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V_th shift. The stressing time needed for V_th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I_DS as stressing V_DS increased, for a given on-state stressing V_GS. Off-state gate–drain stressing resulted in logarithmic positive V_th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V_th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.     

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO₂) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n⁺-polySi) gate. The analysis utilizes the measured gate current density J_G at high oxide fields E_ox in 5.4 to 12 nm thick SiO₂ films between 25 and 300℃. The leakage current measured up to 300℃ was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n⁺-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO₂ conduction band (CB). It was observed that PF emission current I_PF dominates FN electron tunneling current I_FN at oxide electric fields E_ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO₂ films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.