A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOSregister file

A two-write-port, six-read-port, 32×64-bit register file has been designed for 2.5-V 0.5-μm CMOS technology, using primary self-resetting CMOS (SRCMOS) circuit techniques. The register cell are completely level-sensitive scan design test compatible. The fabricated register file occupies an area of 1.84×1.55 mm², and the cell size is 21.6×30 μm². The high-performance register file is implemented in a multiblock structure consisting of subarrays and associated multiplexing circuits. For a given read port, the outputs of all multiplexer circuits are dotted together to form a single global output. A quasi-global approach is used for reset pulse generation and timing control circuits to reduce area overhead. The output pulse width is controlled by a chopper circuit. The write-port operation is achieved by the combination of static data input and dynamic control circuits. The write-path circuits employ the advantages of the input isolation technique. Individual write-enable pulses applied to respective input ports of a multiport register-file cell are effective to establish a priority among those input ports. The present design provides an effective input isolation/decoupling circuit technique that allows the input pulse widths to vary over a wide range. This allows the write operation to be insensitive to control pulse widths, resulting in an effective input isolation scheme. Testing has shown all eight ports to be functional. The measured read access time was 1.1 ns, and read operation has been obtained at cycle times as short as 1.9 ns. The register file has been shown to be tolerant to a very wide range of input pulse widths yet delivers tightly controlled outputs     

CMOS集成电路中电源和地之间的ESD保护电路设计

讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明：在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通．因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。     

A programmable microsystem using system-on-chip for real-time biotelemetry

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.     

Whole-chip ESD protection design with efficient VDD-to-VSS ESDclamp circuits for submicron CMOS VLSI

A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV     

冒险共振现象及其在CMOS电路最大功耗估计中的应用

随着集成电路工艺的不断提高，CMOS电路规模不断增大，功耗成为集成电路设计主要指标之一。文章首先以多位比较器为例，阐述了存在于部分多位电路功能块中的冒险共振现象；然后给出其在VLSI电路最大功耗估计中的应用。ISCAS85电路集实验结果证实了文章思路的有效性。     

A 0.3-mW/Ch 1.25 V Piezo-Resistance Digital ROIC for Liquid-Dispensing MEMS

A low-power multichannel CMOS digital read-out IC (ROIC) for differential piezo-resistive sensing is presented as part of the positioning system of a liquid dispensing MEMS. New very low-voltage and single-battery compatible CMOS circuits are proposed for digital gain tuning, pre-amplification, and integrating A/D conversion. Overall low-power consumption is achieved by operating the key devices in subthreshold in order to prevent from heating the fluidic MEMS. A complete quad-channel ROIC has been integrated in 0.35- $mu{hbox {m}}$ CMOS 2-polySi 4-metal technology. The reported experimental results agree with the electrical simulations.      

A 1.6-GHz dual modulus prescaler using the extendedtrue-single-phase-clock CMOS circuit technique (E-TSPC)

The implementation of a dual-modulus prescaler (divide by 128/129) using an extension of the true-single-phase-clock (TSPC) technique, the extended TSPC (E-TSPC), is presented. The E-TSPC consists of a set of composition rules for single-phase-clock circuits employing static, dynamic, latch, data-precharged, and NMOS-like CMOS blocks. The composition rules, as well as the CMOS blocks, are described and discussed. The experimental results of the complete dual-modulus prescaler, implemented in a 0.8 μm CMOS process, show a maximum 1.59 GHz operation rate at 5 V with 12.8 mW power consumption. They are compared with the results from other recent implementations showing that the proposed E-TSPC circuit can reach high speed with both smaller area and lower power consumption     

A CMOS multichannel IC for pulse timing measurements with 1-mVsensitivity

A multichannel data acquisition circuit that measures the occurrence times of input pulses relative to a 62.5-MHz clock has been integrated in a 1.2-μm CMOS technology. The pulse timing measurement channels are sensitive to input pulses with peak amplitudes as small as 1 mV. Each channel consists of a wideband preamplifier, a tail-cancellation filter, a timing discriminator with time-walk compensation, and a time digitizer. A phase-locked loop (PLL) reference for the time digitizer is included in the circuit. An overall channel timing error of 0.46 ns RMS has been achieved, with negligible channel-to-channel crosstalk, at a power dissipation of 50 mW/channel     

New grounded passive elements-based external multiplier-less memelement emulator to realize the floating meminductor and memristor

A novel memelement emulator configuration has been reported in the presented work. This proposed configuration can be used to realize the function of a floating meminductor as well as the memristor element through proper selection of employed passive elements. The presented emulator circuit is based on MVDCC (modified VDCC) and OTA, which are CMOS implemented electronically tunable ABBs (Active Building Blocks). The designed circuit employs only two ABBs and three grounded passive elements. As per the knowledge of the authors, no such emulation configuration with a floating architecture has been reported so far, which can realize the behaviour of two mem-elements without the use of any external multiplier IC/circuitry, passive inductor or mutation through any externally employed memelement. It can be considered as a notable design feature along with its other advantages like electronically/resistively tunable emulated response and use of only grounded passive elements. Moreover, proposed circuit has been investigated for the consideration of non-idealities and different port parasitics of employed blocks. For the verification purpose, PSPICE simulation environment with CMOS 0.18 µm TSMC technology parameters, has been selected. The functioning of the realized meminductive and memristive behaviour has also been verified through the application example circuits designed using developed emulator circuit. Afterwards, the commercial IC based realization of the proposed emulator circuit has been shown and experimental results are discussed.

     

Wireless monitoring of electrode-tissues interfaces for long term characterization

The electrode-tissues interface (ETI) is one of the key issues for the safety, reliability and efficiency of implantable devices such as stimulators and sensors. The aim of this paper is to report an integrated circuit (IC) that was designed as part of an implantable telemetry device to monitor the ETI. The proposed system performs various types of measurements, such as impedance spectroscopy, cyclic voltammetry, and galvanostatic double pulse method. Hence, the evolution of various electrochemical parameters of the ETI such as complex impedance, faradic resistance, double layer capacity, rheobase current, and chronaxy time, could be monitored long time after implantation. Deviation from nominal impedance for example could indicate electrodes faults as well as nerve conduction changes. The full custom IC has been designed and fabricated with the CMOS 0.18 μm technology. The circuit occupies a silicon area of 2 mm², and consumes less than 3 mW during measurements. Characterisation and in-vivo experimental results validate the full functionalities of the implantable monitoring system including the custom IC.     

An instantaneous response CMOS optical receiver IC with widedynamic range and extremely high sensitivity using feed-forwardauto-bias adjustment

An instantaneous response CMOS optical-receiver IC is described with wide input dynamic range and high sensitivity. In a TCM (time compression multiplexing)-TDMA (time division multiple access) fiber-optic subscriber system, a receiver should be able to handle burst-data packets with different amplitude. This requires quick response and a wide dynamic range. Instantaneous response is achieved with a new feed-forward auto-bias adjustment technique. In addition, multistaged offset compensation provides a wide dynamic range without any external elements and adjustments. Using these design techniques, an optical receiver IC was fabricated in a standard 0.8-μm CMOS technology. The receiver has a wide dynamic range of more than 25 dB for burst-mode optical input at 29 Mb/s. It has high transimpedance gain of 150 dBΩ and high sensitivity of -42 dBm with stable operation for FET threshold voltage and power supply voltage fluctuation     

On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.     

Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit

The greatinformation processing power of human being' s neural systems has attract-ed a lotof attention of those who are dedicated to the implementation of Artificial NeuralNetworks(ANNs) ,which are expected to be of the same computat...     

A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC

Source-synchronous double-data-rate (DDR) signaling is widely used in electrical interconnects to eliminate clock recovery and to double communication bandwidth. This paper describes the design of a parallel optical transceiver integrated circuit (IC) that uses source-synchronous DDR optical signaling. On the transmit side, two 8-b electrical inputs are multiplexed, encoded, and sent over two high-speed optical links. On the receive side, the procedure is reversed to produce two 8-b electrical outputs. The proposed IC integrates analog vertical-cavity surface-emitting lasers (VCSELs), drivers and optical receivers with digital DDR multiplexing, serialization, and deserialization circuits. It was fabricated in a 0.5-$mu$m silicon-on-sapphire (SOS) complementary metal–oxide–semiconductor (CMOS) process. Linear arrays of quad VCSELs and photodetectors were attached to the proposed transceiver IC using flip-chip bonding. A free-space optical link system was constructed to demonstrate correct IC functionality. The test results show successful transceiver operation at a data rate of 500 Mb/s with a 250-MHz DDR clock, achieving a gigabit of aggregate bandwidth. While the proposed DDR scheme is well suited for low-skew fiber-ribbon, free-space, and waveguide optical links, it can also be extended to links with higher skew with the addition of skew-compensation circuitry. To the authors' knowledge, this is the first demonstration of parallel optical transceivers that use source-synchronous DDR signaling.     

CMOS/SOS集成电路输入保护电路设计

本文描述了一种CMOS/SOS集成电路输入保护电路的设计方法。根据保护电路原理,计算了不同保护电路的保护能力,并用实验加以证实。     

A 1.5-ns access time, 78-μm2 memory-cell size, 64-kbECL-CMOS SRAM

A 1.5-ns access time, 78-μm² memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers     

CMOS wireless transceivers: the new wave

A new generation of wireless transceivers is being intergrated into CMOS IC technology, which so far has been used mainly to realize digital and mixed analog-digital baseband circuits. This article reviews some of the RF CMOS circuit design techniques, and shows how an understanding of the strengths and weaknesses of these circuits influences choice of radio architecture. The CMOS approach to radio design calls for the elimination of discrete components in favor of high levels of on-chip integration which freely use translators and mix analog and digital functionality; in these respects, it departs from traditional RF circuit practices. Successful wireless devices of the future will require that radio system design evolve around these new trends in RF integration     

ECL-CMOS and CMOS-ECL interface in 1.2-μm CMOS for 150-MHzdigital ECL data transmission systems

The design of a full-CMOS circuit that converts voltage signals from those used for emitter-coupled logic (ECL) to CMOS and vice versa, for use in digital data transmissions with clock frequencies up to 150 MHz, is described. Extremely high performances are obtained due to a novel circuit principle, in both the ECL-to-CMOS convertor and the CMOS-to-ECL convertor. A wideband CMOS amplifier used in the ECL-to-CMOS convertor, incorporating a current injection technique to increase the bandwidth of the circuit, is also presented. A circuit principle is presented to realize an extremely fast CMOS-to-ECL conversion, based on a current switching technique and charge injection to compensate the large output capacitance. Both circuits make use of replica biasing to ensure maximum switching speed in the ECL-to-CMOS convertor and correct ECL output levels in the CMOS-to-ECL convertor. An ECL-CMOS-ECL repeater has been designed in a 1.2-μm double-metal CMOS process     

Effect of IC layout on the reliability of CMOS amplifiers

With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs.     

Design of a sensorless commutation IC for BLDC motors

This paper presents the design and realization of a sensorless commutation integrated circuit (IC) for brushless DC motors (BLDCMs) by using mixed-mode IC design methodology. The developed IC can generate accurate commutation signals for BLDCMs by using a modified back-EMF sensing scheme instead of using Hall-effect sensors. This IC can be also easily interfaced with a microcontroller or a digital signal processor (DSP) to complete the closed-loop control of a BLDCM. The developed sensorless commutation IC consists of an analog back-EMF processing circuit and a programmable digital commutation control circuit. Since the commutation control is very critical for BLDCM control, the proposed sensorless commutation IC provides a phase compensation circuit to compensate phase error due to low-pass filtering, noise, and nonideal effects of back-EMFs. By using mixed-mode IC design methodology, this IC solution requires less analog compensation circuits compared to other commercially available motor control ICs. Therefore, high maintainability and flexibility can be both achieved. The proposed sensorless commutation IC is integrated in a standard 0.35-/spl mu/m single-poly four-metal CMOS process, and the realization technique of this mixed-mode IC has been given. The proposed control scheme and developed realization techniques provide illustrative engineering procedures for the system-on-a-chip solution for advanced digital motor control. Simulation and experimental results have been carried out in verification of the proposed control scheme.