反熔丝FPGA配置算法与软件实现

反熔丝FPGA制造困难且多用在特殊用途领域,因此有关其位流文件的研究很少.本文首先介绍了反熔丝FPGA及FPGACAD软件流程,接着描述了反熔丝FPGA具体结构并通过一个具体例子说明了如何配置反熔丝FPGA,然后讨论了反熔丝FPGA的编程方法,由此引出了位流文件的格式和反熔丝单元编程信息格式,最后提出了反熔丝FPGA位流文件生成算法并在实验平台实现了该算法.     

反熔丝FPGA配置电路的研究

反熔丝FPGA的编程过程是对可编程逻辑模块进行配置的过程,具体过程是利用配置电路对连接在逻辑模块输入、输出端口的反熔丝单元施加高压,将其击穿形成连接通路,从而使得逻辑模块连接在信号线上.位流数据控制配置电路完成反熔丝单元的预充电、寻址、加压以及编程过程.通过控制晶体管的打开和关断及复用编程通道,可以实现不同类型反熔丝的编程,并简化配置电路的设计规模.测试结果表明,配置电路可靠地完成了反熔丝的编程功能.     

用于可编程器件的MTM反熔丝特性研究

基于ONO（Oxide-Nitride-Oxide）和MTM（Metal-to—Metal）反熔丝技术的可编程存储及逻辑器件已经广泛应用于空间技术中。MTM反熔丝以其单元面积小、集成度高、反熔丝电容小和编程后电阻小等优势,更加适合深亚微米集成电路。文章通过制备MTM反熔丝单元,对单元的击穿特性和漏电性能展开研究,给出了反熔丝单元漏电流与单元尺寸的关系,对单元的编程电流和编程后的电阻值关系进行了研究,与文献[1]给出的Ron=Vf/Ip的关系基本一致。     

MTM反熔丝单元的辐照特性研究

对MTM反熔丝单元的总剂量辐照特性进行了研究,对未编程和编程后两种状态的反熔丝单元在不同电压偏置条件下进行总剂量辐照(Co~(60)-γ射线),辐照总剂量为2 Mrad(Si)。辐照试验结果显示,未编程状态下的MTM反熔丝单元的电压-电流特性曲线基本保持不变,漏电流变化率小于10%。编程后反熔丝单元的电阻特性保持不变,并且编程电阻大小对辐照试验结果无显著影响。试验结果表明,MTM反熔丝单元的抗总剂量(Co~(60)-γ射线)辐照能力达到2 Mrad(Si)以上。     

基于STM32的反熔丝器件编程器设计与实现

反熔丝器件编程需要专门的编程器.针对国内某反熔丝器件,本文介绍了以微处理器STM32F103ZET6为核心的反熔丝器件编程器的设计.该编程器主要由通信电路模块和反熔丝器件编程电路模块组成.通信电路模块包括JTAG程序下裁调试电路、RS232串口通信电路;反熔丝器件编程电路模块包括数模转换电路、信号放大电路、输出缓冲电路、电流检测电路.该编程器结构简单、成本低廉,用户界面友好.实际编程实验表明,该编程器可高效地实现对反熔丝器件的各项编程功能.     

MTM反熔丝单元编程特性研究

主要研究了编程参数对MTM反熔丝单元编程特性的影响,包括编程电压、编程电流、编程次数等。结果表明在满足最低编程电压条件下,编程电压的增大对反熔丝编程电阻无显著影响。编程电流对编程电阻的影响较大,编程电流越大,反熔丝编程电阻越小。编程次数的增多可减小编程电阻,但离散性增大。     

反熔丝FPGA线长驱动布局算法

针对反熔丝FPGA的结构特点,提出了一种线长驱动的反熔丝FPGA布局算法.该算法基于VPR的模拟退火布局算法,针对反熔丝FPGA垂直布线资源有限的特点,提出了新型的成本函数并在CAD实验平台上予以实现.实验结果表明,与VPR布局算法相比,该方法不仅优化了线网总长度,使得线网总长度平均减少了12%,同时还减少了编程的通路反熔丝数目.     

一种应用于反熔丝FPGA的电荷泵电路

电荷泵（Charge Pump）电路以其可成倍输出自身输入电压的特性而被广泛应用于各种芯片的驱动电路中。在反熔丝FPGA中,反熔丝为高压一次编程器件,在编程过程中需要通过高压隔离管将反熔丝与其它器件隔离开,而高压隔离管在工作时需要大于芯片电源VCCA的电压来驱动,如何提供高压保证隔离管能够无损传输数据是反熔丝FPGA研发时必须要考虑的问题。本文提出了一种应用于反熔丝FPGA的电荷泵电路,电路具有快速启动的特点,同时电路工作频率可调,通过在电路中增加冗余NMOS结构,提高了电路在工作中的安全性,该电路在工作时能保证熔丝编程过程中除了反熔丝以外的其他器件不受编程电压的影响,且在编程结束后通过电荷泵输出电压打开隔离管完成信号的无损传输,能够满足反熔丝FPGA对于电荷泵的需求。     

应用于OTP单元的高可靠性MTM反熔丝特性

主要研究了一种新型MTM反熔丝结构的电特性,未编程反熔丝漏电和击穿以及编程特性,有助于电路的编程电流设计,也为反熔丝击穿和漏电的标准制定提供参考。该研究对电极和温度特性的应用也有十分重要的意义。     

基于非晶态铌酸锌铋薄膜的新型反熔丝器件

本文提出了一种基于非晶态铌酸锌铋（a-BZN）介质材料的新型反熔丝器件并对其性能特征进行了研究。考察了a-BZN反熔丝器件的关态特性,选用从上至下的编程方向对反熔丝器件进行击穿,其击穿电压约为6.56V。获得了a-BZN反熔丝器件的关态电阻,约为1GΩ。表征分析了击穿后的a-BZN反熔丝器件的表面形貌。研究了a-BZN反熔丝器件的编程特性以及编程后的开态特性,结果表明a-BZN反熔丝器件所需编程时间约为0.46ms,编程后其开态电阻约为26.1Ω。对比分析了a-BZN反熔丝器件与结晶态铌酸锌铋（cp-BZN）反熔丝器件和栅氧反熔丝器件在性能特征等方面的差异。     

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated     

Long term storage reliability of antifuse field programmable gate arrays

Field Programmable Gate Arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve long operating life, there is a requirement to store un-programmed antifuse FPGA parts for long periods and program them when necessary to support the system. No study on the long term reliability of un-programmed antifuse FPGAs in the storage environment is reported in literature. In this paper, antifuse structures, programming process, and failure mechanisms of antifuse FPGAs are discussed. A failure modes, mechanisms and effects (FMMEA) analysis was performed for storage conditions and critical failure mechanisms were identified. High temperature storage tests of a select number of antifuse FPGAs were performed to accelerate the identified failure mechanisms. These parts were subsequently programmed and yield data was analyzed to determine the effects of high temperature storage.     

Characteristic voltage of programmed metal-to-metal antifuses

The characteristic voltage V_f of different programmed metal-to-metal antifuses was measured and found to be nearly independent of the electrode materials. An electrothermal model, used previously to predict programmed silicon-electrode antifuse resistance, was extended to explain the above phenomenon. The metal-to-metal antifuse resistance vs. the programming current is governed by the Wiedeman-Franz Law     

An antifuse EPROM circuitry scheme for field-programmable repair inDRAM

An antifuse EPROM and 3-V programming circuit has been demonstrated in an existing 0.22-μm DRAM process technology and is fully compatible with 64-Mb SDRAM specifications. The antifuse circuitry uses an internal high-voltage generator for programming and a dynamic sense and static latch scheme that appropriately enables redundant DRAM address decoders at power-up. For efficient high voltage generation, a high-voltage-tolerant capacitor structure was formed by using the high fringing capacitance available between intralevel and interlevel polysilicon and metal lines. Furthermore, the programmable EPROM element was realized without any process modifications by utilizing destructive dielectric breakdown of the thin, highly reliable oxide-nitride-oxide (ONO) dielectric in the basic DRAM cell capacitor structure. This antifuse EPROM circuit enables implementation of field-programmable DRAM features such as memory repair, output impedance matching, and data encryption     

Scaled dielectric antifuse structure for field-programmable gatearray applications

A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1×10¹² s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N⁺ antifuse structures     

A sublithographic antifuse structure for field-programmable gatearray applications

The authors demonstrate an antifuse structure with a cell area of 0.2×0.2 μm² which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2-μm lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse     

An architecture for electrically configurable gate arrays

An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described. The architecture is extensible, and can provide a level of integration comparable to mask-programmable gate arrays. This is accomplished by using a conventional gate array organization with rows of logic modules separated by wiring channels. Each channel contains segmented wiring tracks. The overhead needed to program the antifuses is minimized by an addressing scheme that utilizes the wiring segments, pass transistors between adjacent segments, shared control lines, and serial addressing circuitry at the periphery of the array. This circuitry can also be used to test the device prior to programming and observe internal nodes after programming. By providing sufficient wiring tracks segmented into carefully chosen lengths and a logic module with a high degree of symmetry, fully automated placement and routing is facilitated     

FPGAs achieve superior speed and density with antifuse advancements

FPGAs based on low-resistance, low-capacitance “antifuse” programmable elements offer very high-speed performance with small, cost-effective die sizes for high-volume production applications. FPGA vendors continue to invest in this technology to push further into the performance and density/cost realm previously dominated by conventional mask programmed ASICs. These high-performance, high-density antifuse based products will further distance themselves in speed, cost, and ease-of-use from slower, more costly RAM-based FPGAs.     

512-Mb PROM with a three-dimensional array of diode/antifuse memory cells

A 512-Mb one-time-programmable memory is described, which uses a transistorless two-terminal memory cell containing an antifuse and a diode. Cells are fabricated in polycrystalline silicon, stacked vertically in eight layers above a 0.25-/spl mu/m CMOS substrate. One-time programming is performed by applying a high voltage across the cell terminals, which ruptures the antifuse and permanently encodes a logic 0. Unruptured antifuses encode a logic 1. Cells are arranged in 8-Mb tiles, 1 K rows by 1 K columns by 8 bits high. The die contains 72 such tiles: 64 tiles for data and eight tiles for error-correcting code bits. Wordline and bitline decoders, bias circuits, and sense amplifiers are built in the CMOS substrate directly beneath the memory tiles, improving die efficiency. The device supports a generic standard NAND flash interface and operates from a single 3.3-V supply.