一种宽光谱响应的双结单光子雪崩二极管

基于180 nm BCD工艺提出了一种新型双结雪崩区的单光子雪崩二极管（SPAD）探测器,采用N阱/高压P阱/N+埋层结构形成了两个垂直堆叠的PN结,高压P阱和N+埋层交界面形成较深的主雪崩区,增强对近红外短波光子的探测概率;同时,N阱/高压P阱之间形成浅的次雪崩区,实现对蓝绿光的高效探测,两结同时工作能够有效扩展器件的光谱响应范围。TCAD仿真结果表明,与传统的P阱/深N阱结构相比,双结SPAD器件在300～940 nm的宽光谱范围内有更高的光子探测概率,在800 nm近红外短波段探测概率达到了20.6%。在3 V过偏压下,暗计数率为0.8 kHz,后脉冲概率为3.2%。     

室温下高探测效率InGaAsP/InP单光子雪崩二极管

我们描述了一种高性能平面InGaAsP/InP单光子雪崩二极管（SPAD）,该二极管具有单独的吸收、分级、电荷和倍增（SAGCM）异质结构。通过电场调节和缺陷控制,SPAD在293 K的门控模式下工作,光子探测效率（PDE）为70%,暗计数率（DCR）为14.93 kHz,后脉冲概率（APP）为0.89%。此外,在死区时间为200 ns的主动淬灭模式下工作时,室温下实现了12.49%的PDE和72.29 kHz的DCR。     

p-well/DNW单光子雪崩二极管保护环的最小化设计

随着CMOS工艺特征尺寸的不断减小,探测器本身的大小成为进一步缩小CMOS单光子雪崩二极管(SPAD)阵列的障碍。为了进一步缩小SPAD探测器的尺寸,基于0.18 μm CMOS 图像传感器(CIS)工艺对p-well/DNW(deep n-well)SPAD的保护环尺寸进行设计,并制造了不同保护环尺寸的SPAD器件。测试结果表明,保护环尺寸减小到0.4 μm仍然能有效防止器件发生过早边缘击穿(PEB),且保护环尺寸大于0.4 μm的SPAD器件雪崩击穿电压为16 V,并表现出良好的雪崩击穿特性。此外,保护环尺寸对p-well/DNW SPAD器件的暗计数(DCR)和光子探测概率(PDP)影响较小,直径为20 μm的SPAD器件,温度为25 ℃时暗计数率为638 Hz,且波长为530 nm时峰值光子探测概率为16%,具有低的暗计数率特性和宽的光谱响应特性。     

（英）STI埋层的高光电流和低暗计数率单光子雪崩二极管

本文研究和分析了一种0.18-μm CMOS工艺单光子雪崩二极管（SPAD）,其结构能抑制过早的边缘击穿（PEB）,同时获得较大的光电流和低的暗计数率（DCR）。该SPAD由p-well/deep n-well的感光结,deep n-well向上扩散形成的区域和边缘Shallow Trench Isolation（STI）共同形成的保护环组成。通过测试确定了与光电流和暗率有关的STI层的大小。结果证明,在STI层与保护环之间的重叠区域为1-μm 时,SPAD的暗计数率和光电流最佳。此外,直径为10-μm的圆形SPAD器件的暗计数率为208Hz,且在波长为510nm时峰值光子探测概率为20.8%,此时具有低的暗计数率和高的探测效率以及宽的光谱响应特性。     

低暗计数率InGaAsP/InP单光子雪崩二极管

通过对InGaAsP/InP单光子雪崩二极管（SPAD）的探测效率、暗计数率等基本特性与该器件的禁带宽度、电场分布、雪崩长度、工作温度等参数之间关系的分析,采用比通常的InxGaAs （x=0.53）材料具有更宽带隙的InxGa1-xAsyP1-y（x=0.78,y=0.47）材料作为光吸收层,并且精确控制InP倍增层的雪崩长度,有效地降低了SPAD的暗计数率。其中InGaAsP材料与InP材料晶格匹配良好,可在InP衬底上外延生长高质量的InGaAsP/InP异质结,InGaAsP材料的带隙为Eg=1.03 eV,截止波长为1.2 m,可满足1.06 m单光子探测需要。同时,通过设计并研制出1.06 m InGaAsP/InP SPAD,对其特性参数进行测试,结果表明,当工作温度为270 K时,探测效率20%下的暗计数率约20 kHz。因此基于时间相关单光子计数技术的该器件可在主动淬灭模式下用于随机到达的光子探测。     

一种低暗计数率CMOS单光子雪崩二极管

基于标准0.18μm CMOS工艺设计了一种新型单光子雪崩二极管(SPAD)器件。该SPAD以p-well/n-well轻掺杂雪崩结作为器件的核心工作区域,同时利用三个相邻n阱间的横向扩散在pn结边缘形成n-虚拟保护环以提高器件的性能。采用Silvaco软件对该器件的电场分布、响应度、击穿电压、光子探测效率和暗计数率等性能参数进行了仿真分析。仿真结果表明:当SPAD器件的光窗口直径为20μm且n阱间隙宽度为1.4μm时,其雪崩击穿电压为13V;在过偏压为1V时,其探测效率峰值和暗计数率分别为37%和0.82kHz;在450~700nm波长范围器件的响应度较好,且在500nm处达到峰值0.33A/W。     

基于CMOS工艺的单光子雪崩二极管的盖革模式仿真

采用互补金属氧化物半导体(CMOS)工艺和p阱保护环,使用SILVACO公司的ATLAS软件进行器件结构设计和仿真,得到了能正常工作在盖革模式下的单光子雪崩二极管(SPAD)。仿真结果表明:设计的器件结构中p+/n-阱结降低了结附近的电场强度,并且低于平面pn结的电场强度,从而起到了抑制二极管发生边缘击穿的保护作用;电场强度和碰撞产生率呈正相关,并得出了电子、空穴的雪崩产生率与纵向位置的关系曲线及器件中某一个点处的电子雪崩产生率和偏置电压的关系曲线。仿真结果对基于CMOS工艺的SAPD结构设计具有一定的指导意义。     

高边缘击穿和扩展光谱的圆形单光子雪崩二极管（英文）

介绍了一种0. 18μm互补金属氧化物半导体(CMOS)技术的新型宽光谱荧光相关谱探测器,其为高边缘击穿、扩展光谱和低暗计数率的圆形单光子雪崩二极管(SPAD).该器件由p+/deep n-well结,p-well保护环和多晶硅保护环组成.通过Silvaco TCAD 3D器件仿真,直径为10μm的圆形p+/deep n-well SPAD器件具有较高边缘击穿特性.此外,p+/deep n-well结SPAD比p+/n-well结SPAD具有更长的波长响应和扩展光谱响应范围.该器件在0. 5 V过量偏压下,可在490～775 nm波长范围内实现超过40%的光子探测率.该圆形p+/deep n-well SPAD器件在25℃时具有较好雪崩击穿为15. 14 V,具有较低暗计数率为638 Hz.     

雪崩击穿特性的高压硅二极管

叙述了具有雪崩击穿特性的高压二极管的设计及一次全扩散工艺概况以及实际应用的效果。     

近红外1550 nm单光子探测器硬件电路设计

针对现有单光子探测器模块价格昂贵和体积大的不足,设计了基于 InGaAs／InP 雪崩光电二极管（APD）的便携式单光子探测器,给出了探测器温控模块和偏置电压源的设计电路,门控信号的产生和雪崩信号的提取由 FPGA 完成。实验结果表明：在200 MHz 门控条件且制冷温度为－55℃时,探测器的最大光子探测效率（PDE）约为16％,当探测效率为12％时,暗计数率（DCR）约为8．2×10－6／ns。     

一种单光子雪崩光电二极管主动淬火电路

We present a novel gated operation active quenching circuit （AQC）. In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I-V characteristic measurement resuits of the detector. The circuit integrated with a ROIC （readout integrated circuit） is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications.     

Study of the influence of virtual guard ring width on the performance of SPAD detectors in 180 nm standard CMOS technology

The influence of the virtual guard ring width (GRW) on the performance of the p-well/deep n-well single-photon avalanche diode (SPAD) in a 180 nm standard CMOS process was investigated. TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1 μm. It is experimentally found that, compared with an SPAD with GRW = 2 μm, the dark count rate (DCR) and afterpulsing probability (AP) of the SPAD with GRW = 1 μm is significantly increased by 2.7 times and twofold, respectively, meanwhile, its photon detection probability (PDP) is saturated and hard to be promoted at over 2 V excess bias voltage. Although the fill factor (FF) can be enlarged by reducing GRW, the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling (TAT) effect in the 1 μm guard ring region. By comparison, the SPAD with GRW = 2 μm can achieve a better trade-off between the FF and noise performance. Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.     

Readout schemes for low noise single-photon avalanche diodes fabricated in conventional HV-CMOS technologies

Three different pixels based on single-photon avalanche diodes for triggered applications, such as fluorescence lifetime measurements and high energy physics experiments, are presented. Each pixel consists of a 20 μm×100 μm (width×length) single photon avalanche diode and a monolithically integrated readout circuit. The sensors are operated in the gated mode of acquisition to reduce the probability to detect noise counts interferring with real radiation events. Each pixel includes a different readout circuit that allows to use low reverse bias overvoltages. Experimental results demonstrate that the three pixels present a similar behavior. The pixels get rid of afterpulses and present a reduced dark count probability by applying the gated operation. Noise figures are further improved by using low reverse bias overvoltages. The detectors exhibit an input dynamic range of 13.35 bits with short gated ‘on’ periods of 10 ns and a reverse bias overvoltage of 0.5 V. The three pixels have been fabricated in a standard HV-CMOS process.