Self-alignment of 6,13-bis(triisopropylsilylethynyl)pentacene molecules through magnetic flux-affected nanoparticle motion in solution-processed transistors

We propose a viable method of inducing the self-alignment of 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene) molecules using magnetic nanoparticles under a controlled magnetic field. An essential feature of the self-alignment of TIPS-pentacene containing magnetic nanoparticles is systematically studied through meticulous understanding of gradient solvent evaporation in a magnetic nanoparticle-dispersed droplet guided by a static magnetic field. It is found that such TIPS-pentacene molecules are spontaneously aligned by magnetic flux-affected nanoparticle motion with the generation of gradual anisotropic solvent evaporation. In particular, by controlling the effective magnetic force applied to a magnetic nanoparticle-containing TIPS-pentacene solution, TIPS-pentacene droplet flow can be induced, causing greater alignment. We fabricate TIPS-pentacene-based transistors to confirm the effect of this aligned state on device performance, using both optical and electrical methods.     

Electrical stability of pentacene thin film transistors

The influence of environmental conditions on the device operation and the stability of polycrystalline pentacene thin film transistors (TFTs) were investigated. Electrical in-situ and ex-situ measurements of staggered pentacene TFTs were carried out to study the influence of dry oxygen and moisture on the device stability. The transistors were fabricated by organic molecular beam deposition on thermal oxide dielectrics. Oxygen exposure of the pentacene films lead to the creation of acceptor-like states in the bandgap. The acceptor-like states cause a shift of the onset of the drain current towards positive gate voltages. The charge carrier mobility and the on/off ratio of the transistor are not affected by the acceptor-like states. Furthermore, the acceptor-like states have an influence on the stability of the TFTs. Devices exposed to oxygen exhibit a shift of the threshold voltage upon prolonged biasing. Transistors characterized under vacuum conditions (no oxygen exposure) do not exhibit a shift of the threshold voltage (bias stress effect) as a consequence of prolonged biasing. The experimental results show a clear correlation between the device behavior upon oxygen exposure and the stability of the devices. The shift of the onset voltage upon oxygen exposure correlates with the shift of the threshold voltage upon prolonged bias. The influence of dry oxygen on the onset voltage, the threshold voltage, and the electrical stability will be described. Furthermore, the influence of bias stress on the operation of organic circuits like an active matrix addressed OLED displays will be discussed.     

Bottom-contact organic field-effect transistors based on single-crystalline domains of 6,13-bis(triisopropylsilylethynyl) pentacene prepared by electrostatic spray deposition

Large crystalline domains (a few hundred micrometers in size) of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) were prepared by electrostatic spray deposition (ESD) and used as the active layers of bottom-contact organic field-effect transistors. The TIPS pentacene active layers were directly patterned via a shadow mask in the ESD process. The device, which had a 5-μm-long channel composed of a single-crystalline domain, exhibited a high field-effect mobility of more than 0.1 cm²/V s but resulted in a high threshold voltage of −17 V. The threshold voltage could be lowered to −6.4 V by reducing the thickness of the BC electrodes from 30 to 10 nm; this threshold voltage lowering was probably due to an improvement in the charge injection from the source electrode to the active layer.     

High-performance thin-film transistor with 6,13-bis(triisopropylsilylethynyl) pentacene by inkjet printing

We have studied the performance improvement of organic thin-film transistor (OTFT) with a solution based TIPS pentacene (6,13-bis(triisopropylsilylethynyl)pentacene) by inkjet printing. The TIPS pentacene with 1.0 wt.% solution in 1,2-dichlorobenzene was used for printing of an active layer of OTFT. The OTFT printed at room temperature shows a shoulder-like behavior but it disappears for the OTFT printed at the substrate temperature of 60 °C. The OTFT on plastic exhibited an on/off current ratio of ∼10⁷, a threshold voltage of −2.0 V, a gate voltage swing of 0.6 V/decade and a field-effect mobility of 0.24 cm²/Vs in the saturation region.     

High operational stability of solution-processed organic field-effect transistors with top-gate configuration

Electrical characteristics of top-gate field-effect transistors based on a wide range of solution-processed organic semiconductors are systematically investigated. The top-gate field-effect transistors based on different organic semiconductors—from an amorphous polymer semiconductor to a polycrystalline molecular semiconductor—exhibit higher operational stability compared with bottom-gate organic field-effect transistors reported in literature, in spite of significant difference in field-effect mobility. The correlation between charge transport and operational stability is discussed to gain insight into high operational stability of top-gate organic field-effect transistors.     

Photoinduced negative magnetoresistance in 6,13-bis(triisopropylsilylethynyl)-pentacene field-effect transistors

We report on photoinduced negative organic magnetoresistance in low external magnetic-fields (<100 mT) in 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-Pentacene) field-effect transistors. An external magnetic field does not influence the dark current of our device. In contrast, there is a significant increase in photocurrent when magnetic field is applied to the irradiated device, which leads to negative magnetoresistance. The magnetoresistance and photoresponse values are strongly correlated and both are influenced by applied voltages and irradiation intensity. We attribute the observed photoinduced negative magnetoresistance in TIPS-Pentacene field-effect transistors to the presence of electron-hole pairs under irradiation. The overall dissociation probability of electron-hole pairs rises under the influence of an external magnetic field, which leads to a higher number of free charge carriers.     

Pentacene bottom-contact thin film transistors with solution-processed BZT gate dielectrics

The solution-processed high-k barium zirconate titanate (BZT) as gate dielectrics for bottom-gate pentacene-based organic thin film transistor (OTFT) applications is presented. To reduce the transistor threshold voltage, higher work function metals (Au) is used as the gate electrodes. The threshold voltage is efficiently decreased from −3.6 to −2.15 V as compared to that of Al. In addition, the UV/ozone was employed to treat the Au (source/drain) surface to improve the poor crystalline of pentacene grown on Au. Moreover, the surface morphologies and orientations of pentacene films were analyzed through atomic force microscopy (AFM) and X-ray diffraction. As the results, the stack of pentacene molecules from disorder state changed to vertical growth on the Au surface. Finally, the electrical properties of pentacene-based thin film transistors exhibit high field-effect mobility of 4.5 cm²/V·s, low subthreshold swing of 260 mV/decade, high on/off ratio of 1.4 × 10⁵ and low operation voltage of −5 V. These results are better than the reported data using bottom contact pentacene OTFTs.     

In situ modification of low-cost Cu electrodes for high-performance low-voltage pentacene thin film transistors (TFTs)

We demonstrate low-voltage pentacene thin film transistors (TFTs) using in situ modified low-cost Cu (M-Cu) as source–drain (S/D) electrodes and solution-processed high capacitance (200 nF/cm²) gate dielectrics. Under a gate voltage of ?3 V, the device with M-Cu electrodes shows a much higher apparent mobility (1.0 cm²/V s), a positively shifted threshold voltage (?0.62 V), a lower contact resistance (0.11 MΩ) and a larger transconductance (12 μS) as compared to the device with conventional Au electrodes (corresponding parameters are 0.71 cm²/V s, ?1.44 V, 0.41 MΩ, and 5.7 μS, respectively). The enhancement in the device performance is attributed to the optimized interface properties between S/D electrodes and pentacene. Moreover, after encapsulation the M-Cu electrodes with a thin layer of Au in the aim of suppressing unfavorable surface oxidation, the electronic characteristics of the device are further improved, and highly enhanced apparent mobility (2.3 cm²/V s) and transconductance (19 μS) can be achieved arising from the increased conductivity of the electrode itself. Our study provides a simple and feasible approach to achieve high performance low-voltage OTFTs with low-cost S/D electrodes, which is desirable for large area applications.     

Effects of film microstructure on the bias stability of pentacene field-effect transistors

In this report, the effects of film microstructure on the bias stability of pentacene field-effect transistors (FETs) were investigated. To control the microstructure of pentacene film, substrate temperature was changed from 25 to 90 °C during pentacene deposition. As the substrate temperature increased, pentacene grain size increased (or grain boundary (GB) decreased) because of the elevated surface diffusion of pentacene molecules. Accordingly, field-effect mobility increased up to 1.52 cm²/V. In contrast, bias stability showed totally different characteristics: samples prepared at high substrate temperatures exhibited the lowest degree of bias stability. This GB independent charge trapping phenomenon was solved by examining molecular scale ordering within the intragrain regions. The pentacene film grown at 90 °C showed the largest percentage of pentacene molecules with bulk crystalline structures. This inhomogeneity in the pentacene microstructure induces crystal mismatch within intragrain region, thereby providing deep trap sites for gate-bias stress driven instability. Our study shows that GB is not the main sites for bias stress related charge trapping, rather the molecular orientation within intragrain region is responsible for the charge trapping events. In this regard, the control of molecular scale ordering is important to obtain OFETs with a high bias stability.     

A tunable organic inverter based on groove patterned pentacene thin film transistors using soft-contact lamination

Organic zero drive load inverters based on pentacene thin film transistors with periodic groove patterned dielectrics are fabricated using nanoimprinting and soft-contact lamination methods. Depletion mode transistor behavior is achieved when the current direction is parallel to groove direction and enhancement mode transistor behavior is achieved when the directions are crossed. An organic inverter is created after connecting two soft-contact laminated transistors. The electrical performance of the drive transistor can be varied and the organic inverter is tunable. This is done by utilizing a PDMS stamp with the source-drain electrode and changing the angle between the current direction and groove direction. The gain and symmetry of the VTC is improved by using an enhancement mode transistor where the source-drain electrode formed by thermal evaporation instead of being a soft contact-laminated device.     

High performance of pentacene organic thin film transistors by doping of iodine on source/drain regions

Contact doping was conducted by iodine in a top contact configuration in a pentacene organic thin film transistor (OTFT), to investigate its effects on contact resistance and the resulting electrical performance. Iodine doping in the pentacene film caused the change of pentacene structure, thus leading to an increase in electrical anisotropy, i.e. ratio of lateral to vertical resistivity. The two resistive components of doped pentacene film underneath the Au contacts were major contributors to the contact resistance, and a model to explain the dependence of contact resistance on iodine doping was presented. Finally, OTFTs fabricated on iodine doped source/drain contacts exhibited high mobility of 1.078 cm²/V s, two times that of OTFTs with undoped contacts, due to the low contact resistance.     

Self-patterning of high-performance thin film transistors

We have developed a technique for the preparation of thin film transistors (TFTs) through the self-patterning of various organic and inorganic materials via solution processing using a wide range of solvents. To obtain selectively self-patterned layers, we treated the oxide dielectric with two-phase patterned self-assembled monolayers of hexamethyldisilazane (HMDS) and octyltrichlorosilane. The conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonic acid) in water and the dielectric polymer poly(vinyl phenol) in propylene glycol methyl ether acetate were both selectively deposited and patterned on the HMDS regions with high-quality feature shapes. When source and drain electrodes were patterned on the bottom-gate oxide wafer, we also self-patterned organic and inorganic semiconductors around the channel (HMDS) regions. These TFT devices exhibited moderate to good electronic characteristics. This method has great potential for the economical full solution processing of large-area electronic devices. The selectivity in the patterning phenomena can be understood in terms of surface energy interactions.     

Dielectric surface-polarity tuning and enhanced operation stability of solution-processed organic field-effect transistors

The electrical performance of triethylsilylethynyl anthradithiophene (TES-ADT) organic field-effect transistors (OFETs) was significantly affected by dielectric surface polarity controlled by grafting hexamethyldisilazane and dimethyl chlorosilane-terminated polystyrene (PS-Si(CH₃)₂Cl) to 300-nm-thick SiO₂ dielectrics. On the untreated and treated SiO₂ dielectrics, solvent–vapor annealed TES-ADT films contained millimeter-sized crystals with low grain boundaries (GBs). The operation and bias stability of OFETs containing similar crystalline structures of TES-ADT could be significantly increased with a decrease in dielectric surface polarity. Among dielectrics with similar capacitances (10.5–11 nF cm⁻²) and surface roughnesses (0.40–0.44 nm), the TES-ADT/PS-grafted dielectric interface contained the fewest trap sites and therefore the OFET produced using it had low-voltage operation and a charge-carrier mobility ∼1.32 cm² V⁻¹ s⁻¹, on–off current ratio >10⁶, threshold voltage ∼0 V, and long-term operation stability under negative bias stress.     

Electronic characterization of double-gate thin film transistors

A method of determining the electronic parameters, i.e. the free charge carrier density, the surface state density and the bulk trap state density, of the semiconductor in double-gate thin film transistors is described. The method is based on a comparison of the calculated field-effect conductance with the observed drain current of the device. The theory is formulated such that it applies even though the semiconductor is thin compared with the effective Debye lengths. An illustrative example of the method applied to a CdSe double-gate thin film transistor is given.     

Effects of traps on thin film transistors

Trap effects on Weimer-type thin film transistors (TFT) were studied. Measurements of thermally stimulated current (TSC), temperature dependence of drain current and MOS structure capacitance were performed to study trap distribution in TFT's. It was found that the steady state Fermi level lies near to the conduction band (0·1–0·05 eV) in the TFT. Only those traps lying near or above the Fermi level can affect the performance of TFT. Drain current relaxation effects for a step-gate voltage, and drain current hysteresis for a sine-wave gate voltage, were studied as trap effects on TFT performance. These phenomena were interpreted in terms of trap kinetics, and the roles of traps in the insulator film and in the semiconductor film were identified. The energy depth, density and cross section of traps affecting TFT performance were estimated.     

Fabrication of organic thin film transistors on Polyethylene Terephthalate (PET) fabric substrates

In this paper organic thin film transistors (OTFTs) are directly fabricated on fabric substrates consisting of Polyethylene Terephthalate (PET) fibers. A key process is coating the polymer layers on the fabric in order to reduce the large surface roughness of the fabric substrate. Two polymers, i.e. polyurethane (PU) and photo-acryl (PA), are used to reduce the large surface roughness and simultaneously improve the process compatibility of the layers with the subsequent OTFTs processes while also retaining the original flexibility of the fabric. The surface roughness of the PU/PA-coated fabric is significantly reduced to 0.3 μm. Furthermore, the original flexibility of the PET fabric remained after coating of the PU/PA polymer layers. The mobility of the OTFTs fabricated on the PU-PA coated fabric substrate is 0.05 ± 0.02 cm²/V s when three PA layers and 90 nm thick pentacene layer were used. The performance does not vary even after 30,000 bending test.     

Influence of channel layer and passivation layer on the stability of amorphous InGaZnO thin film transistors

The electrical stability of amorphous InGaZnO (a-IGZO) TFTs with three different channel layers was investigated. Compared with the single channel layer, the a-IGZO TFT with double stacked channel layer showed the lowest threshold voltage shift with slightly change in field effect mobility and sub-threshold swing under positive and negative gate bias stress tests. Moreover, sputtered SiN_x thin film was served as passivation layer where the V_th shift in bias stress effect evidently became less. It was found that the passivated a-IGZO TFT with double stacked channel layer still exhibited the best stability. The results prove that the stability of a-IGZO TFTs can be effectively improved by using double stacked channel layer and passivation layer.     

Electrical evaluation of thin film CdS diodes and transistors

Thin film active devices are of current interest to semiconductor electronics, since their integration with passive thin film components will eventually lead to a new concept in circuitry for microelectronics. This paper reports on electrical performances of thin film active devices fabricated entirely by vacuum vapor deposition techniques. CdS is used for the semi-insulating material. Thin film diodes show space-charge-limited current properties which are modified by the presence of traps. Experimental data on thin film transistors are in good agreement with theory for the insulated-gate field effect transistor. The theory predicts current-voltage and gain-bandwidth capability of the device.