ATM shared-memory switching architectures

ATM will provide flexibility in bandwidth allocation and will allow a network to carry heterogeneous services ranging from narrowband to wideband services. The challenge is to build fast packet switches able to match the high speeds of the input links and the high performance requirements imposed. The CCITT has standardized the asynchronous transfer mode (ATM) as the multiplexing and switching principle for the broadband integrated services digital network (B-ISDN). ATM is a packet and connection-oriented transfer mode based on statistical time division multiplexing techniques. The information flow is organized in fixed-size packets called cells, consisting of a user information field (48 octets) and a header (5 octets). The primary use of the header tag is to identify cells belonging to the same virtual channel and to make routing possible. Cell sequence on a virtual channel is preserved, a very low cell loss probability must be guaranteed (< 10^-12), and intensive error and flow control protocols are provided at the edges of the network     

突发信道下无线ATM的前向差错控制方案

在无线ATM网络中，无线信道的高误码率和突发特性要求对无线ATM信元进行较强的误码保护。本文提出了一种有效的前向差错控制（FEC）方案，对信元头采用较强的FEC，对信息域采用较弱的FEC，并针对信道特性和采用的前向差错控制编码的特点进行元头信元内交织，文中对无线ATM信元在突发信道下的信元丢失率和信元信息错误率进行了分析，仿真结果表明该方案在降低信元信息错误率的同时有效地降低了信元丢失率。     

An adaptive FEC scheme for data traffic in wireless ATM networks

A new adaptive forward-error-correction scheme (AFEC) is introduced at the link layer for TCP/IP data traffic in wireless ATM networks. The fading and interference in wireless links cause high and variable error rates, as well as bursty errors. The purpose of the AFEC scheme is to provide a dynamic error-control mechanism by using Reed-Solomon coding to protect the ATM cell payload, as well as the payload type indicator/cell loss priority fields in the ATM cell header. In order to enhance the error tolerance in cell framing and correct delivery, the AFEC scheme functions within a new concept called LANET framing and addressing protection mechanisms. The AFEC scheme has been validated using a simulation testbed of a low-speed wireless ATM network     

A novel delineation mechanism for the ATM adaptation layer 2 over wireless ATM networks

The ATM adaptation layer 2 (AAL2) has been standardized by the ITU‐T for the support of low data rate and delay‐sensitive applications, such as voice, over ATM networks. One of the main characteristics of the AAL2 standard is the support for multiplexing information at the expense of introducing a new frame structure inside the payload of the ATM cells. The AAL2 standard introduces a mechanism for the delineation of the AAL2 packets and it has been found that the delineation mechanism reduces the performance of AAL2 in the presence of channels with high bit error rates. In this paper, a novel delineation mechanism is proposed for AAL2 to be used over highly error‐prone channels, such as wireless links. The proposed mechanism improves the performance (i.e. reduces packet loss) of the AAL2 standard in the presence of bit errors and in some cases reduces the overhead required for the delineation of the AAL2 packets. Copyright © 2002 John Wiley & Sons, Ltd.     

Error detection and correction options for data services in B-ISDN

The authors investigate error detection and correction options for data services in the broadband integrated services digital network (B-ISDN). They discuss and analyze different options for error detection and correction by considering the various alternatives ranging from no error protection to only error detection. Based on the analysis and results presented, a per-cell cyclic redundancy check (CRC) has been adopted in the adaptation layer for all data services. The authors focus on the ATM (asynchronous transfer mode) adaptation layer (AAL) error protection alternatives available within the framework of a per-cell CRC. The ATM cell header and AAL fields are described. A 4 bit cell sequence number for detecting cell misordering is analyzed. Based on the analysis, it is concluded that the 4 bit sequence number provides a powerful capability for detection of cell misordering     

Mechanism for shaping the emitted traffic at ATM terminal‐points

A mechanism for controlling the emitted traffic to asynchronous transfer mode (ATM) network, system design and implementation architectures are introduced. Specifically, the effective rate of a stream, defined under certain multiplexing conditions and quality‐of‐service specifications, is enforced to desired values by controlling the cell emission rate of the generated bursts. The traffic shaping mechanism is closely associated to an ATM transmitter, which is mainly responsible for ATM cell assembly and header error control. The mechanism has been designed to support data communication services. The whole system has been implemented as a VLSI circuit. Copyright © 2002 John Wiley & Sons, Ltd.     

Cell discard and TDMA synchronization using FEC in wireless ATMsystems

The asynchronous transfer mode (ATM) employs header-error control (HEC) to protect the ATM cell header from bit error and/or avoid the misforwarding of ATM cells. However, wireless ATM systems require a more powerful forward-error correction (FEC) scheme to offer acceptable bit-error rate (BER) performance. This paper proposes the utilization of FEC, which makes it possible to discard ATM cells more reliably. Time-division multiple-access (TDMA) is very suitable for wireless ATM systems. In the TDMA scheme, synchronization is very important. This paper also proposes to combine FEC with unique word (UW) detection for improving TDMA synchronization characteristics     

An experimental ATM switch for BISDN studies

This paper describes the architecture, functionality and performance of an experimental ATM switch being developed at the Telecom Australia Research Laboratories as part of its investigations into the broadband ISDN. The proposed switch architecture consists of parallel omega networks preceded by a Batcher bitonic sorting network. The switching fabric has no internal cell buffering. Cell buffering is provided only on the switch outputs for cells simultaneously contending for the same output port. The switch fabric and cell buffers include mechanisms for providing prioritized servicing of queued cells and prioritized discarding of cells based on priority fields contained within the cell header. Components of the switch are currently being implemented in 2 μm CMOS VLSI.     

An integrated FEC coding scheme for ATM transmission over regenerative satellite networks

The application of asynchronous transfer mode (ATM) on both wireless and satellite networks requires system adaptation. This adaptation has to improve the overall system's performance, and achieve high quality‐of‐service classes approaching that for fibre‐optic communications. In this paper, a new integrated forward‐error‐correction (FEC) coding scheme is introduced for ATM transmission over regenerative satellite networks. The proposed FEC scheme is a concatenation of two Reed–Solomon codes tailored for the header and payload parts of the ATM cell. This integrated coding scheme is shown to significantly improve the cell loss ratio as compared to the standard CRC code used in the ATM cell header. We obtain both upper and lower performance bounds for the concatenated code and check their accuracy when compared to exact system's performance. Both analytical and simulation results show that a cell loss ratio and bit‐error rate (BER) of 10^?25 and 10^?7 can be, respectively, achieved with minimum delay requirements on the SATCOM link. Finally, an approximation for the system's throughout is obtained. It is shown that using a hybrid selective‐repeat automatic‐repeat‐request (SR‐ARQ) with the RS code, a large throughput of approximately 0.843 can be achieved at BERs lower than 10^?7 for data services. Copyright © 2005 John Wiley & Sons, Ltd.     

A 16×622 Mb/s ATM switch: PRELUDE switch architectureintegrated into a 6-million transistor monochip

This paper presents the integration of the Prelude switch architecture into a monochip ATM switch, COM16M, capable of handling 16 multiplexes carrying ATM cells at 622 Mb/s. It is a fully autonomous switch, i.e., the chip includes clock adaptation, routing, and cell buffering as well as header translation and control capabilities. The switch is integrated into one single chip containing 6000000 transistors implemented in a 0.5-μm CMOS process     

A shared-memory virtual channel queue for ATM broadband terminal adaptors

In order to take advantage of the low entry cost of the future public ATM (asynchronous transfer mode) network with shared facilities, it is highly desirable to interconnect different hosts and local area networks (LANs) to the ATM network. The interface between the computer hosts or LANs and the ATM network, commonly called a broadband terminal adaptor (BTA), provides the necessary format conversion for the data packets and the ATM cells. It is conceivable that multiple packets from different virtual channels are interleaved as they arrive at the receive-end BTA. The BTA must have a sufficiently large buffer, called a virtual channel queue (VCQ), to temporarily store the partially received packets. Once a complete packet has been received, it is forwarded to the host or LAN. Whenever the buffer fills with all incomplete packets, a packet must be discarded to make room for others. In this paper, we first study, through computer simulations, the buffer size requirement of a shared-memory VCQ for different numbers of virtual channels at various packet loss probabilities. We then present two different implementation architectures for the shared-memory VCQ, and compare their hardware complexity. The second architecture with linked-queue approach, adopted in our work, requires less buffer and has better scalability to accommodate a large number of virtual channels. Various possible error conditions, such as cell losses in the ATM network and the VCQ buffer overflow, are considered. Corresponding solutions are proposed and included in the VCQ designs.     

Design and applications of ATM LAN/WAN adapters

ATM networks are today operational, both as backbones for existing LAN technologies and as commercial wide-area multiservice networks. Still, in the early deployment of multi-site ATM networks, a number of difficulties have arisen out of the differences between the service definitions in local ATM networks and long-distance carrier networks. In particular, the adaptation of LAN emulation protocols relying on switched, best-effort connections to the first generation of ATM WAN services turned out to require the introduction of specific functions. In this paper, we study and discuss the nature of these adaptation functions which include peak rate shaping in order to comply with the traffic contract at the public UNI, efficient buffering and selective cell discarding to optimize the performance of end-to-end data protocols and fairness mechanisms to improve resource sharing. We describe a flexible hardware platform which enabled a quick prototyping of these functions. It provides on-board support for efficient cell processing and for associated functions (rate control, buffering, etc.). The use of a cell processor enables a software-only implementation of the ATM cell handling, yielding short development times and easy debugging while being compatible with an operation at line speeds up to 155 Mbit/s. We finally give examples and measurements of the use of the adapters in LAN/WAN interworking situations. This revised version was published online in August 2006 with corrections to the Cover Date.     

A fast parallel-tree switch architecture for ATM networks

In this paper we present a novel fast packet switch architecture based on Banyan interconnection networks, called parallel-tree Banyan switch fabric (PTBSF). It consists of parallel Banyans (multiple outlets) arranged in a tree topology. The packets enter at the topmost Banyan. Internal conflicts are eliminated by using a conflict-free 3 × 4 switching element which distributes conflicting cells over different Banyans. Thus, cell loss may occur only at the lowest Banyan. Increasing the number of Banyans leads to a noticeable decrease in cell loss rate. The switch can be engineered to provide arbitrarily high throughput and low cell loss rate without the use of input buffering or cell pre-processing. The performance of the switch is evaluated analytically under uniform traffic load and by simulation, under a variety of asynchronous transfer mode (ATM) traffic loads. Compared to other proposed architectures, the switch exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources. The advantages of PTBSF are modularity, regularity, self-routing, low processing overhead, high throughput and robustness, under a variety of ATM traffic conditions. © 1998 John Wiley & Sons, Ltd.     

Theoretical Performance Analysis of Sliding Window Flow Control

A transmitter breaks a message up into packets and transmits the packets to a receiver over a single virtual circuit within a local area network. The receiver has a finite amount of storage capacity for buffering messages. A sliding window protocol turns the transmitter on and off to ensure there is always storage room in the receiver for packets. Mean throughput rate and delay statistics are studied as a function of model parameters.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

A prototype broadcast-and-select photonic ATM switch with a WDMoutput buffer

A rack-mounted prototype of a broadcast-and-select (B and S) photonic ATM switch is fabricated. This switch has an optical output buffer utilizing wavelength division multiplexed (WDM) signals. The WDM technology solves. The cell-collision problem in a broadcast-and-select network and leads to a simple network architecture and the broadcast/multicast function. The prototype can handle 10-Gb/s nonreturn-to-zero (NRZ) coded cells and 5-Gb/s Manchester-coded cells and has a switch size of four. In this prototype, the level and timing design are key issues. Cell-by-cell level fluctuation is overcome by minimizing the loss difference between the optical paths and adopting a differential receiver capable of auto-thresholding. The temperature control of delay lines was successful in maintaining the phase synchronization. Using these techniques, we are able to provide a WDM highway with a bit error rate of less than 10^-12. Fundamental photonic ATM switching functions, such as optical buffering and fast wavelength-channel selection, are achieved. We show our experimental results and demonstrate the high performance and stable operation of a photonic ATM switch for use in high-speed optical switching systems as an interconnect switch for a modular ATM switch and an ATM cross-connect switch     

Preventing internal and external conflicts in an input buffering reverse baseline ATM switch

When two or more packets that are destined to the same output of an ATM switch arrive at different inputs, buffers at inputs or outputs are used to queue all but one of these packets so that external conflict is prevented. Although input buffering ATM switches are more economical and simpler than output buffering ATM switches, significant loss of throughput can occur in input buffering ATM switches due to head‐of‐line (HOL) blocking when first‐in–first‐out (FIFO) queueing is employed. In order to avoid both external conflict and alleviate HOL blocking in non‐blocking ATM switches, some window‐based contention resolution algorithms were proposed in the literature. In this paper, we propose a window‐based contention resolution algorithm for a blocking ATM switch based on reverse baseline network with content addressable FIFO (CAFIFO) input buffers. The proposed algorithm prevents not only external conflicts but also internal conflicts, in addition to alleviating HOL blocking. This algorithm was obtained by adapting the ring reservation algorithm used on non‐blocking ATM switches to a reverse baseline network. The fact that a non‐blocking network is replaced by a log₂ N‐stage reverse baseline network yields a significant economy in implementation. We have conducted extensive simulations to evaluate the performance of reverse baseline network using the proposed window‐based contention resolution algorithm. Simulation results show that the throughput of reverse baseline network can be as good as the throughput of non‐blocking switches if the window depth of input buffers is made sufficiently large. Copyright © 2000 John Wiley & Sons, Ltd.     

A pipelined, multiprocessor architecture for a connectionlessserver for broadband ISDN

The direct provision of connectionless service in BISDN calls for servers that are connected to or are part of an ATM network to provide the routing function at input speeds up to 622 Mb/s. Routing is achieved in such a server by changing the VCI/VPI headers in the ATM cells; actual switching is done by existing switches in the ATM network. The paper presents an architecture capable of executing all the functions of a server at input speeds up to 622 Mb/s, scalable to multiple inputs at that speed, making use of processors and special hardware that are available today. To avoid storing large quantities of data, the architecture routes data packets by examining routing information in the initial cell of the packet and routing subsequent cells as they arrive rather than waiting until the complete packet has arrived. It is capable of handling packets that have been multiplexed at the SAR sublayer using AAL Type 3/4 and, with minor modifications, could also handle Type 5 traffic. Arguments are also presented for the use of AAL Type 5 for the direct connectionless service     

Performance issues in VC-merge capable switches for multiprotocollabel switching

In a multiprotocol label switching (MPLS) domain, ATM label-switching routers (LSRs) are potentially capable of providing the highest forwarding capacity in the backbone network. Virtual circuit (VC) merging is a mechanism in an ATM-LSR that allows many IP routes to be mapped to the same VC label and provides a scalable mapping method that can support thousands of destinations. VC merging requires reassembly buffers so that cells belonging to different packets intended for the same destination do not interleave with each other. In this paper, the impact of VC merging on the buffering requirement for the reassembly buffers is investigated. We propose a realistic architecture that supports VC merging. We study the performance of this architecture using an analytic approach and using simulation driven by empirical Internet packet-size distribution. At the cell level, our main finding indicates that VC merging incurs a minimal overhead compared to non-VC merging, in terms of additional buffering. Moreover, the overhead decreases as utilization increases or as the traffic becomes more bursty with longer dependence. The finding has important practical consequences since routers and switches are dimensioned for high utilization and stressful traffic conditions. At the packet level, VC merging generally achieves a higher goodput than non-VC merging with EPD for the same buffer size. We also study the delay performance and find that the additional delay due to VC merging is insignificant at high speed     

A reflective semiconductor optical amplifier based all-optical header separator

An all-optical header extraction scheme based on the reflective semiconductor optical amplifier (RSOA) is presented, which can be used to process variable-length and bit-rate transparent packets. Through selecting the appropriate carrier-lifetime of the RSOA, the payload pulses obtain smaller gains than header pulses and are considered to be compressed. By using the reflective structure, the header pulses can acquire larger gains than the payload twice, and the contrast radio (CR) is improved. The simulation results show that the CRs can reach 22.8 dB and 18 dB for the packets with header pulses at the rates of 2.5 Gb/s and 10 Gb/s, respectively, and these values can be optimized through properly selecting the structure parameters, such as the small-signal gain and saturation energy.