Practical realisation of mod p, p prime multiplier

A practical realisation of a mod p, p prime multiplier for the case p = 2n?2k+1, k相似文献   

Design of most-significant-bit-first serial multiplier

The design of a two's complement most-significant-bit-first add and shift serial multiplier is presented. In this multiplier, one of the multiplicands is represented in full length, whereas the second multiplicand is presented in a bit-serial fashion with the most significant bit (MSB) first     

Design of a C-testable booth multiplier using a realistic fault model

A Booth multiplier is the most widely used type of multiplier. In this article, the testability issues involved in its design are discussed. In contrast to previous work, the fault model includes not only node stuck-at faults, but also transistor stuck-open and stuck-close faults. Moreover, as a result of adopting a hierarchical testability approach, the designed Booth multiplier turns out to be fully C-testable. To achieve this C-testability, only three additional controllable inputs are required, which results in a negligible area and delay overhead.Currently with Alcatel Bell Telephone.     

Design and implementation of a new four-quadrant MOS analog multiplier

A four-quadrant MOS analog multiplier is proposed using the quarter-square technique, which is based on the quadratic characteristics of an MOS transistor operating in the saturation region and the difference operation of four identical sourced-coupled differential amplifiers. The multiplier has a simple configuration and a large dynamic range over a wide frequency range, since each input signal passes only one transistor to reach the output. The operation of the multiplier was analyzed in detail, and the second-order effects were also analyzed. The proposed circuit was fabricated in 12-V p-well CMOS process with a 5-m minimum feature. The measured results show that linearity error is less than 1% for 5-V_p-p input at ±5 V supply voltage, and the-3 db bandwidth is 30 MHz.     

Design of a CMOS low-power and low-voltage four-quadrant analog multiplier

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications.     

一种用于PFC的模拟乘法器设计

为了实现变频控制,产生一个与输入信号同频同相的电压信号,使输入电流跟随输入电压,设计了一种基于BCD工艺的模拟乘法器,并阐述了该电路设计的工作原理和结构.该乘法器应用于电流控制的功率因素校正电路,具有0～3 V的输入信号范围,采用上华0.6 μm BCD工艺设计,并用Cadence spectre仿真器进行仿真.仿真结果表明,输出波形是一个半正弦波,并且和输入同频同相,幅度达到1.2 V.     

基于16位定点DSP的并行乘法器的设计

设计了一种用于1 6位定点DSP中的片内乘法器.该乘法器采用了改进型Booth算法,使用CSA构成的乘法器阵列,并采用跳跃进位加法器实现进位传递,该设计具有可扩展性,并提出了更高位扩展时应改进型方向.设计时综合考虑了高性能定点DSP对乘法器在面积和速度上的要求,具有极其规整的布局布线.     

Design of an LDO with capacitor multiplier

This paper presents a low quiescent current,highly stable low-drop out(LDO) regulator.In order to reduce capacitor value and control frequency response peak,capacitor multipliers are adopted in the compensation circuit with mathematic calculations.The phase margin is adequate when the load current is 0.1 or 150 mA.Fabricated in an XFAB 0.6μm CMOS process,the LDO produces 12.2 mV(0.7%) overshoot voltage while the current changes at 770 mA/100μs with a capacitor load of 10μF.     

Design of ternary adiabatic multiplier on switch-level

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be obtained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ternary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are characterized with distinctive low power consumption.     

一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。     

Design of low-error fixed-width modified booth multiplier

This paper presents an error compensation method for a modified Booth fixed-width multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 35% reduction in area and power consumption of a multiplier compared with the ideal multiplier.     

基于电容倍增的LDO设计

本文设计了一种低静态电流、高稳定性的低压降线性稳压器,为了减小补偿电容值,及控制频率响应中尖峰的位置,本文采用了电容倍增技术进行频率补偿,并给出了稳定性的理论推导。该LDO在负载电流0.1mA和150mA时都具有较好的相位裕度。电路采用XFAB 0.6um CMOS工艺模型,最终设计的LDO电路静态功耗17uA。使用10uF的负载电容,在负载电流变化率为770mA/100us时,最大过冲为12.2mV（0.7%）。     

Design strategies for optimal hybrid final adders in a parallel multiplier

In this paper we address the problem of adding twon-bit numbers when the bit arrival times are arbitrary (but known in advance). In particular we address a simplified version of the problem where the input arrival times for theith significant bits of both addends are the same, and the arrival timest _i have a profile of the form: $$t_0 \leqslant t_1 \leqslant \cdot \cdot \cdot< t_k = t_{k + 1} = \cdot \cdot \cdot = t_p > t_{p + 1} \geqslant \cdot \cdot \cdot \geqslant t_{n - 1} $$ This profile is important because it matches the signal arrival time profile of the reduced partial products in a parallel multiplier before they are summed in the final adder. In this paper we present a design strategy specific to arrival time profiles generated by partial product reduction trees constructed by optimal application of the Three Dimensional Method presented by Oklobdzija, Villeger, and Liu and subsequently analyzed by Martel, Oklobdzija, Ravi, and Stelling. This strategy can be used to obtain adders for any arrival time profile that matches the above form, as well as a broad class of arrival time profiles where even greater variation in the input times is allowed. Finally, we show that our designs significantly out-perform the standard adder designs for the uniform signal arrival profile, yielding faster adders that (for these profiles) are also simpler and use fewer gates.     

All n?p?n 4-quadrant analogue multiplier

A technique is described that utilises the addition of logarithms in an all n?p?n bipolar configuration, to derive the algebraic product of two variables. The circuit is ideal for integrated-circuit implementation, and uses a simple method of distortion cancellation that is shown to be independent of device current gain ? and base-spreading resistance.     

丙类倍频器的设计与仿真

基于晶体管丙类功率放大器的原理,设计晶体管丙类倍频器,给出了倍频器中基极偏置电路元件参数设计过程。利用Multisim软件对所设计电路进行了仿真,通过调整LC并联回路的谐振频率实现对输入信号的三倍频,根据输出信号的频谱图提出进一步优化电路的办法。仿真表明应用Multisim软件辅助设计丙类倍频器,可以使电路设计更加直观高效。     

Design and implementation of a high-speed matrix multiplier based on word-width decomposition

This paper presents a flexible 2/spl times/2 matrix multiplier architecture. The architecture is based on word-width decomposition for flexible but high-speed operation. The elements in the matrices are successively decomposed so that a set of small multipliers and simple adders are used to generate partial results, which are combined to generate the final results. An energy reduction mechanism is incorporated in the architecture to minimize the power dissipation due to unnecessary switching of logic. Two types of decomposition schemes are discussed, which support 2's complement inputs, and its overall functionality is verified and designed with a field-programmable gate array (FPGA). The architecture can be easily extended to a reconfigurable matrix multiplier. We provide results on performance of the proposed architecture from FPGA post-synthesis results. We summarize design factors influencing the overall execution speed and complexity.     

基于AD9850的倍频器设计

介绍基于直接数字频率合成器（DDS）AD9850的倍频器设计，倍频倍数N可以在限定范围内自行设置。系统主要模块CPLD/FPGA、DDS（AD9850）和单片机（80C51）之间可以并行通信，具有编程控制简便、接口简单、成本低、易于实现系统小型化等优点。在定时、算法精确的前提下，倍频后的波形平均精度达到10^-3。     

Design of low-error fixed-width multiplier for DSP applications

A low-error design of the fixed-width parallel multiplier for digital signal processing (DSF) applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit, product with lower relative product errors, but uses only about half the area of a standard parallel multiplier. These features make it very suitable for use in many DSP applications such as arithmetic coding, wavelet transformation, digital filtering     

Applications of a four-quadrant multiplier

Applications demonstrating the performance of a four-quadrant multiplier and signal switch in controlled-feedback modes are presented. The range of possible applications of the circuit is greatly increased by considering this mode of operation over previously suggested applications.