Realization of multiple valued logic and memory by hybrid SETMOS architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.     

Novel Hybrid Voltage Controlled Ring Oscillators Using Single Electron and MOS Transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits     

Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SET_s such as the tunnel barrier lowering effect, parasitic MOSFET_s operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFET_s and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADC_s fully accounting for nonideal effects of real SET_s is successfully demonstrated for the first time. Compared with the previous SET-based ADC_s, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability.     

Compact analytical model for room-temperature-operating silicon single-electron transistors with discrete quantum energy levels

A compact and analytical model for silicon single-electron transistors (SETs) considering the discrete quantum energy levels and the parabolic tunneling barriers is proposed. The model is based on a steady-state master equation that considers only the three most probable states derived from ground level and the first excited level for each number of electrons in the dot to reduce the complexity while accounting for the quantum-level spacing and multiple peaks in Coulomb oscillation. Negative differential conductance (NDC) characteristics and aperiodic Coulomb oscillations due to nonuniform quantum-level spacings can be reproduced in this model. The model was compared with measurements, and good agreement was obtained. Simulations of some basic circuits that utilize NDC are successfully carried out by applying our model to the HSPICE circuit simulation. Our model can provide suitable environments for designing CMOS-combined room-temperature-operating highly functional SET circuits.     

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than /spl omega/W; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.     

Measurements of single electron transistor devices combined with aCCC: progress report

The BNM-LCIE is developing a current standard based on single electron transistor (SET) pumps. This paper gives an overview of the experimental set-up. It includes the circuit details, in particular the combination of miniature filters and homemade lines giving high attenuation in a wide frequency band, and a cryogenic current comparator (CCC) with winding ratio of 10000:1 for high accuracy amplification of the current. The results of the testing of the circuit and CCC are presented, together with the first measurements of the current through a SET carried out by means of a CCC. Coulomb blockade oscillations with an amplitude less than 200 fA have been observed with a signal to noise ratio approaching 100 and at bias voltages as small as a 100 nV     

Coulomb blockade of single-electron tunneling,and coherent oscillations in small tunnel junctions

A microscopic approach to the theory of small, current-biased tunnel junctions is developed. This approach yields a natural account of the secondary quantization of both the single-electron (quasiparticle) and Cooper-pair (Josephson) current components. The theory shows that the current of the single electrons is blocked by their Coulomb interaction at low temperatures within a considerable range of the junction voltage. As a result of the blockade, coherent oscillations of the voltage can arise even in the absence of Josephson coupling, e.g., for single-electron tunneling (SET) between normal metal electrodes. The most significant features of these SET oscillations and their coexistence with Bloch oscillations in Josephson junctions are studied in detail. Prospects of experimental verification of the predicted effects and of their possible applications are discussed.     

Coulomb blockade induced negative differential resistance effect in a self-assembly Si quantum dots array at room temperature

We report a Coulomb blockade induced negative differential resistance (NDR) effect at room temperature in a self-assembly Si quantum dots (Si-QDs) array (Al/SiO₂/Si-QDs/SiO₂/p-Si), which is fabricated in a plasma enhanced chemical vapor deposition system by using layer-by-layer deposition and in-situ plasma oxidation techniques. Obvious NDR effects are directly observed in the current-voltage characteristics, while corresponding capacitance peaks are also identified at the same voltage positions in the capacitance-voltage characteristics. The NDR effect in dot array, arising from the Coulomb blockade effect in the nanometer-sized Si-QDs, exhibits distinctive scan-rate and scan-direction dependences and differs remarkably from that in the quantum well structure in the formation mechanism. Better understanding of the observed NDR effect in Si-QDs array is obtained in a master-equation-based numerical model, where both the scan-rate and scan-direction dependences are well explained.     

Observation of negative differential resistance and single-electron tunneling in electromigrated break junctions

We observed a negative differential resistance (NDR) along with single-electron tunneling (SET) in the electron transport of electromigrated break junctions with metal-free tetraphenylporphyrin (H₂BSTBPP) at a temperature of 11 K. The NDR strongly depended on the applied gate voltages, and appeared only in the electron tunneling region of the Coulomb diamond. We could explain the mechanism of this new type of electron transport by a model assuming a molecular Coulomb island and local density of states of the source and the drain electrodes.     

Accurate and computer efficient modelling of single event transients in CMOS circuits

A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate     

Advances in the modeling of single electron transistors for the design of integrated circuit

Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.     

Transport model of controlled molecular rectifier showing unusual negative differential resistance effect

We investigate theoretically the charge accumulated Q in a three-terminal molecular device in the presence of an external electric field. Our approach is based on ab initio Hartree-Fock and density functional theory methodology contained in Gaussian package. Our main finding is a negative differential resistance (NDR) in the charge Q as a function of an external electric field. To explain this NDR effect we apply a phenomenological capacitive model based on a quite general system composed of many localized levels (that can be LUMOs of a molecule) coupled to source and drain. The capacitance accounts for charging effects that can result in Coulomb blockade (CB) in the transport. We show that this CB effect gives rise to a NDR for a suitable set of phenomenological parameters, like tunneling rates and charging energies. The NDR profile obtained in both ab initio and phenomenological methodologies are in close agreement.     

一种SETMOS二阶带通滤波器设计实现

单电子晶体管（SET）作为一种纳电子器件有着较大的优势,将SET与纳米MOS混合构成的器件（SETMOS）是目前研究的热点之一。SETMOS作为一种新的混合器件,在结合了两者优点的同时,具有与SET一样的库仑振荡特性和MOS高增益等特性。文章基于一种sETM0s混合结构的电压电流特性的数学模型,设计并实现了一种SETMOS二阶带通滤波器,阐述了这种SETMOS带通滤波器的结构、工作条件、性能、参数和特点,并用PSpice对其传输特性进行了仿真验证,结果证明,SETMOS在其通带范围内具有良好的带通幅频特性,且具有低电压、低功耗和高频的特点。     

A multi-nano-dot circuit and structure using thermal-noise-assisted tunneling for stochastic associative processing

The single-electron circuit and nanostructure described in this paper are designed for stochastic associative processing, which is an expanded version of ordinary associative memory processing. In stochastic associative processing, the association probability of each stored pattern depends on the similarity between the stored pattern and the input pattern. Such unique processing is useful for sequential stochastic association and for clustering for vector quantization. Conventional single-electron circuits operate only at very low temperature for practical junction capacitance (i.e., 30 K for 0.1 aF) because the charging energy in these circuits is directly related to the tunnel junction capacitance. Our multi-nano-dot circuit and structure operate at room temperature with a junction capacitance around 0.1 aF through tunneling processes assisted by thermal noise. We analyze the operation of this circuit in detail and propose for it a stochastic associative processing operation, where the detection timing of the electron position controls the association probability distribution.     

A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

Observation of room temperature negative differential resistance in multi-layer heterostructures of quantum dots and conducting polymers

Multi-layer heterostructure negative differential resistance devices based on poly-[2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylenevinylene] (MEH-PPV) conducting polymer and CdSe quantum dots is reported. The conducting polymer MEH-PPV acts as a barrier while CdSe quantum dots form the well layer. The devices exhibit negative differential resistance (NDR) at low voltages. For these devices, strong negative differential resistance is observed at room temperature. A maximum value of 51 for the peak-to-valley ratio of current is reported. Tunneling of electrons through the discrete quantum confined states in the CdSe quantum dots is believed to be responsible for the multiple peaks observed in the I-V measurement. Depending on the observed NDR signature, operating mechanisms are explored based on resonant tunneling and Coulomb blockade effects.     

Noise-tolerant quantum MOS circuits using resonant tunneling devices

Resonant tunneling devices are promising candidates for comingling with traditional CMOS circuits, yielding better performance in terms of reduced silicon area, faster circuit speeds, lower power consumption, and improved circuit noise margin. These resonant tunneling devices have several intrinsic merits that include: high current density, low intrinsic capacitance, the negative differential resistance effect, and relative ease of fabrication. In this paper, we briefly describe some circuit configurations of Silicon quantum MOS logic family, with a special emphasis on noise-tolerant design that is now becoming an important constraint for robust and reliable operation of very deep submicron VLSI chips. More specifically, we discuss a novel strategy to incorporate quantum-tunneling devices into mainstream dynamic CMOS circuits with a view to improving the noise immunity of the latter. Dynamic CMOS circuits are rampantly used in modern high-performance VLSI chips achieving the best tradeoff between circuit speed, silicon area, and power consumption. However, they are inherently less noise-tolerant than their static CMOS counterparts. With the continuously deteriorating noise margins due to aggressive down scaling of the CMOS fabrication technologies, the performance overhead due to existing remedial noise-tolerant circuit techniques becomes prohibitively high. In this paper, we propose a novel method that utilizes the negative differential resistance property of quantum tunneling devices. The performance and noise immunity of the proposed circuits are evaluated through both analytical studies and SPICE simulations. We demonstrate that the noise tolerance of dynamic CMOS circuits can be greatly improved with very little degradation in circuit speed. The benefit of the proposed technique is evident even for currently available Silicon-based resonant tunneling devices with a relatively small peak-to-valley current ratio.     

Quantum dots fabricated by selective area MOVPE and their application to single electron devices

A novel method of formation of uniform GaAs quantum dot (QD) structures, using selective area metalorganic vapour phase epitaxy (SA-MOVPE), and their application to single electron transistors (SETs) are demonstrated. The SiN _x -coated substrates having a wire-like opening with three prominences are used. The wire-like opening is aligned in the [110] direction, which corresponds to channel region of SET. AlGaAs/GaAs modulation-doped heterostructures are grown on these substrates. Due to three prominences on the wire, the quasi-one-dimensional electron gas (Q-1DEG) channel, having a periodic variation in its width, are naturally formed. This leads to the formation of a quantum dot near the central prominence and two tunneling barriers beside the dot, which are connected to quantum wires.I _D−V _G characteristics under constant source-drain bias condition show clear conductance oscilations near the pinch-off, and oscillations are observed up to 65 K.I _D−V _DS characteristics measured at 2·1 K show clear Coulomb blockade. The results indicate the formation of SET by SA-MOVPE. Using similar method, resistance-load single electron inverter circuit is also fabricated.     

Impact of Key Circuit Parameters on Signal-to-Noise Ratio Characteristics for the Radio Frequency Single-Electron Transistors

Hybrid simulation was performed to analyze the response of the real-time reflection-type radio frequency single-electron transistor (RF-SET) measurement system. A compact and physically-based analytical SET model, which was validated with a Monte Carlo simulator, was used to simulate the SET characteristics, while SPICE equivalent circuits were implemented to simulate all other components of the RF-SET measurement system. The impact of various key parameters on the RF-SET response was demonstrated for a carrier frequency much less than I/e ( is the typical current through the SET). It was revealed that an inevitable feed-through loss between the tank circuit and the cryogenic amplifier, and high-frequency parasitics of the inductor degrade the RF-SET performance significantly. As such, they have to be optimized to experimentally realize the shot-noise-limited charge sensitivity.