1 V 2 GHz CMOS frequency divider

A new frequency divider, called differential injection locking, is proposed. The proposed divider has no transistor stacking to suppress the performance degradation due to supply voltage reduction. It is shown that the proposed frequency divider achieves 2 GHz with 1 V supply voltage and 540 /spl mu/W power consumption.     

2.4GHz动态CMOS分频器的设计

对现阶段的主流高速CMOS分频器进行分析和比较,在此基础上设计一种采用TSPC(truesingle phase clock)和E-TSPC(extended TSPC)技术的前置双模分频器电路.该分频器大大提高了工作频率,采用0.6μm CMOS工艺参数进行仿真的结果表明,在5V电源电压下,最高频率达到3GHz,功耗仅为8mW.     

10～37GHzCMoS四分频器的设计

给出基于0．13μmCMOS工艺、采用单时钟动态负载锁存器设计的四分频器。该四分频器由两级二分频器级联而成。级间采用缓冲电路实现隔离和电平匹配。后仿真结果表明其最高工作频率达37GHz,分频范围为27GHz。当电源电压为1．2V、工作频率为37GHz时,其功耗小于30mW,芯片面积为0．33-0．28mm2。     

18 GHz low-power CMOS static frequency divider

A pseudo-differential latch circuit is investigated. By removing the current source from the conventional source-coupled field-effect-transistor logic (SCFL) structure, the speed of the circuit can be improved. The pseudo-differential D-type flip-flop-based 2:1 static frequency divider, which can operate up to 18 GHz and consumes less than 4 mA from a 1.8 V supply, has been realised in 0.18 /spl mu/m standard digital CMOS technology.     

50 GHz static frequency divider in 130 nm CMOS

A novel circuit topology and design procedure to increase the operating frequency of current model logic (CML) static frequency dividers is proposed. The topology and design procedure are used to design a 50 GHz CML static frequency divider in 130 nm CMOS. The designed divider has a 20 GHz division bandwidth and consumes 11.7 mW power from a 1.5 V supply.     

1.3 V supply voltage 38 GHz static frequency divider

An ultra-low supply voltage and low power dissipation fully static frequency InP SHBT divider operating at up to 38 GHz is reported. The fully differential parallel current switched configuration of D-latch maintains the speed advantages of CML circuits while allowing full functionality at a very low supply voltage. The frequency divider operates at up to 38 GHz at a single-ended input power of 0 dBm. The power dissipation of the toggled D-flip-flop is 8 mW at a power supply voltage of 1.3 V. The authors believe this is the lowest supply voltage for static frequency dividers around this frequency in any technology. This low power configuration is suitable for any digital integrated circuit.     

GHz programmable counter with low power consumption

A high-speed programmable counter with a new reloadable D flip-flop which integrates the programmable function to a true-single-phase-clock (TSPC) D flip-flop is presented. The proposed reloadable D flip-flop is able to operate at higher frequencies with lower power consumption compared to the performance of the existing bitcell. The programmable divide-by-N counter implemented with this reloadable D flip-flop using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 2 GHz for a 1.8 V supply voltage with 4.7 mW power consumption.     

81.5?85.9 GHz injection-locked frequency divider in 65 nm CMOS

An injection-locked frequency divider (ILFD) using the shunt-series inductive peaking technique is proposed. Fabricated in a 65 nm process, the proposed ILFD and a conventional one have the measured locking range of 81.5-85.9 and 71-77.4 GHz, respectively. Compared with the conventional ILFD, the measured free-running frequency of the proposed one is increased by 12.5 . Both ILFDs have core area of 0.036 mm² and power of 12 mW for a 1.55 V supply without buffers.     

High-speed CMOS frequency divider

A high-speed CMOS frequency divider is proposed. Using fewer transistors and only NMOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes and larger transconductance. A device sizing rule for the maximum input frequency is given. The proposed frequency divider is suitable for high-speed operational while consuming a moderate amount of power     

功耗低、结构紧凑的吞吐脉冲式分频器

本文设计了一个功耗低、结构紧凑的吞吐脉冲式多模分频器电路。为了节省功耗,除2/3双模预分频器中的一个D触发器受模式控制信号MC的控制,在特定模式下能自动关闭。可编程计数器和吞吐脉冲计数器中的D触发器共享以构成紧凑的结构进一步减小功耗。所设计的多模分频器采用标准65nmCMOS工艺实现,面积为28umX22um.当工作频率为988MHz时,1.2V电源电压下的分频器功耗为0.6mW。     

Ultracompact SOI CMOS frequency doubler for low power applications at 26.5-28.5 GHz

In this paper, a complementary metal oxide semiconductor (CMOS) frequency doubler for wireless applications at Ka-band is presented. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90 nm silicon on insulator (SOI) technology. All impedance matching, filter and bias elements are implemented on the chip, which has a very compact size of 0.37 mm/spl times/0.27 mm. At an output frequency of 27 GHz, source/load impedances of 50 /spl Omega/, a supply voltage of 1.25 V, a supply current of 8 mA and an input power of -4.5 dBm, a conversion gain of 1.5 dB was measured. To the knowledge of the authors, the circuit has by far the highest operation frequency for a CMOS frequency multiplier reported to date and requires lower supply power than circuits using leading edge III/V and silicon germanium (SiGe) technologies.     

应用于26 GHz-41 GHz频率综合器的高速可编程分频器的设计

毫米波频率综合器中的重要模块之一高速可编程多模分频器,它主要用于对VCO的输出信号进行分频从而获得稳定的本振信号,它的性能影响整个毫米波频率综合器性能。本文设计的一种高速、低功耗、分频比可变的分频器具有非常重要的意义[1]。根据26 GHz-41 GHz硅基锁相环频率综合器的系统指标,本文基于TSMC 45nm CMOS工艺,设计实现了一种高速可编程分频器。本文采用注入锁定结构分频结构实现高速预分频,该结构可以实现在0 d Bm的输入功率下实现25 GHz-48 GHz的分频范围、最低功耗为:2.6 m W。基于脉冲吞咽计数器的可编程分频器由8/9双模分频器和可编程脉冲吞咽计数器组成。其中8/9双模分频器由同步4/5分频器和异步二分频构成,工作频率范围10 GHz-27 GHz,最低输入幅度为:300 m V,最低功耗为:1.6 m V。可编程吞咽计数器采用改进型带置数功能的TSPC D触发器,该可编程分频器的最大工作范围:25 GHz;最小功耗为:363μW。本文设计的高速可编程多模分频器,可以实现32-2 062的分频比;当工作于28 GHz时,相位噪声小于-159 dBc/Hz。动态功耗为5.2 m W。     

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-/spl mu/m complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.     

A power efficient 26-GHz 32:1 static frequency divider in 130-nm bulk CMOS

A 32:1 static frequency divider consisting of five stages of 2:1 dividers using current mode logic (CML) was fabricated in a 130-nm bulk complementary metal-oxide semiconductor (CMOS) logic process. By optimizing transistors size, high operating speed is achieved with limited power consumption. For an input power of 0dBm, the 32:1 divider operates up to 26GHz with a 1.5-V supply voltage. The whole 32:1 chain including buffers consumes 8.97mW and the first stage consumes only 3.88mW at a 26-GHz operation. The power consumption of the first 2:1 stage is less than 15% of other bulk CMOS static frequency dividers operating at the same frequency.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

1V, 1 GHz 64/65 dual modulus divider in bipolar-SOI

The author describes a 1 V operating logic based on a silicon bipolar-on-insulator process. Demonstration devices include a dual modulus, 64/65 divider operating to 1 GHz, and a 2 GHz prescaler     

83GHz InP DHBT静态分频器

A static frequency divider is presented using 0.7μm lnP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master-slave D-flip-flop topology with 30 HBTs and 20 resistors with a chip size 0.62 ×0.65 mm^2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.     

A miniaturized Wilkinson power divider with CMOS active inductors

A miniaturized Wilkinson power divider implemented in a standard 0.18-/spl mu/m CMOS process is presented in this letter. By using active inductors for the circuit implementation, a significant area reduction can be achieved due to the absence of distributed components and spiral inductors. The power divider is designed at a center frequency of 4.5GHz for equal power dividing with all ports matched to 50/spl Omega/. Drawing a dc current of 9.3mA from a 1.8-V supply voltage, the fabricated circuit exhibits an insertion loss less than 0.16dB and a return loss better than 30dB at the center frequency while maintaining good isolation between the output ports. The active area of the miniaturized Wilkinson power divider is 150/spl times/100/spl mu/m/sup 2/, which is suitable for system integration in monolithic microwave integrated circuit (MMIC) applications.     

5 GHz, 12 mW NMOS frequency divider

Reports on the development of an NMOS 2:1 frequency divider circuit that operates to over 5 GHz. It is powered from a 2.5 V supply and dissipates only 0.012 W. These results indicate that the use of silicon MOS technology may be extended to very-high-speed low-power applications     

A low-voltage,low power divide-by-4 LC-tank injection-locked frequency divider

A low-voltage wide locking range injection-locked frequency divider (ILFD) using a standard 0.18?µm complementary metal-oxide-semiconductor process is presented. The ILFD is based on a differential LC VCO with one injection metal oxide semiconductor field effect transistor (MOSFET) for coupling external signals to the resonator. The low-voltage operation and wide locking range is obtained by boosting the gate voltage swing of the ILFD. Measurements show that at the supply voltage of 0.67?V, the divider's free-running frequency is tunable from 3.91 to 4.22?GHz, and the core power consumption is 1.87?mW. At the incident power of 0?dBm the divide-by-4 operation range is about 2?GHz (12.3%), from the incident frequency 15.3–17.3?GHz. The divide-by-2 locking range is about 5.1?GHz (77%), from the incident frequency 4.1–9.2?GHz.