CCD新型遮光层工艺技术研究

针对内线转移CCD金属铝遮光技术存在的漏光问题,对比了不同难熔金属材料的遮光性能,选择漏光率较低的氮化钛金属作为新型遮光层材料.研究了不同气体配比、不同射频功率和腔体压力对氮化钛刻蚀选择比、条宽控制等参数的影响.通过优化工艺参数,获得了适合于刻蚀氮化钛遮光层的工艺条件.     

一种新的微透镜阵列制作技术

介绍了一种利用光刻、等离子体刻蚀和高温热熔等工艺在PMMA材料上制作折射微透镜的新方法,该方法具有刻蚀工艺容差大、热熔后球冠形貌好、易于和CCD实现工艺集成等优点。经过对各个工艺参数的优化实验,制备出了具有良好球冠形貌的微透镜阵列,并成功与256×256内线转移CCD完成了工艺集成,集成后微透镜阵列的整体形貌和尺寸与设计值相吻合。     

颗粒对CCD光刻图形完整性的影响分析

分析了薄膜淀积工艺、光刻工艺和刻蚀工艺过程中引入的颗粒对光刻图形完整性的影响。采用三相三次多晶硅工艺,光刻制备沟阻或多晶硅时,颗粒阻碍曝光和刻蚀,引起沟阻或多晶硅连条,使CCD的像元划分和信号电子的定向转移遭受破坏,降低器件成品率。     

一种内线转移可见光CCD弥散特性的模拟分析

运用半导体二维数值模拟软件sentaurus TCAD,对基于p型衬底制作的横向抗晕内线转移CCD的弥散特性进行了数值模拟研究,建立了sentaurus TCAD软件模拟横向抗晕内线转移CCD器件仿真模型,对影响器件弥散特性的光敏区n型区域、垂直CCD p阱进行了模拟分析.结果表明,光敏区n型区域注入能量控制在450～550 keV,垂直CCD p阱注入能量控制在200～600 keV,剂量控制在4.0×1012～8.0×1012 cm-2,器件弥散特性最佳.     

双栅氧LDMOS器件工艺技术的研究与改进

双栅氧LDMOS器件刻蚀过程中极易造成多晶硅残留现象,降低了栅极和源区之间的击穿电压.改进了制备双栅氧LDMOS器件的方法,对于70 nm以下的栅氧厚度,采用保留整个厚栅氧器件区域栅氧的刻蚀方法,同时用一次多晶工艺代替二次多晶工艺,消除了多晶硅残留现象,减少了工艺步骤,提高了成品率;对于厚度大于70 nm或者100 nm的厚栅氧器件,除了以上的改进措施,还增加了一步光刻工艺,分别单独形成高压和低压器件的源漏区域.通过这些方法,解决了多晶残留问题,得到了性能更好的LDMOS器件,大大提高了成品率.     

CCD多晶硅刻蚀技术研究

CCD晶硅刻蚀相比于传统CMOS工艺的多晶硅刻蚀需要多晶硅对氮化硅更高的刻蚀选择比,更长的过刻蚀时间.采用Cl2+He,Cl2+He+O2,Cl2+He+O2+HBr三种工艺气体组分在Lam4420机台进行了多晶硅刻蚀实验,研究了不同气体配比、不同射频功率对刻蚀速率、选择比、条宽、侧壁形貌等参数的影响.通过优化工艺参数,比较刻蚀结果,最终获得了适合于CCD多层多晶硅刻蚀的工艺条件.     

823×592元内线转移CCD图像传感器

采用三层多晶硅、埋沟、双层金属工艺研制了1/2英寸823×592、8.3μm×8.3 μm内线转移CCD,该器件设计制作了纵向抗晕结构,实现了内线转移器件光晕抑制.该器件水平驱动频率可达30 MHz,峰值响应波长位于550 nm,动态范围62.6 dB.     

ICP腔体压力对直流偏压的影响

基于GaAs器件干法刻蚀工艺,介绍感应耦合等离子(ICP)的刻蚀原理,以Cl2和BCl3为刻蚀气体,研究分析了在GaAs表面刻蚀工艺中不同的腔体压力下设备直流偏压的变化情况.发现在各种不同的功率下都存在一个特定的腔体压力,当低于该腔体压力时直流偏压会随腔体压力的增大而增加,当高于该腔体压力后直流偏压会随着腔体压力的增加而缓慢减小.讨论了产生这种现象的原因,揭示了其中的物理机理,以该方法作为参考,通过一组对比实验在工艺中得到验证,给出了GaAs刻蚀的工艺条件,为刻蚀工艺条件的优化提供了一个参考.     

刻蚀小尺寸CCD接触孔工艺研究

采用CF4,CHF3,Ar三种工艺气体进行小尺寸CCD接触孔刻蚀实验,研究了不同气体配比、不同射频功率对刻蚀速率、选择比、条宽控制、侧壁形貌等参数的影响。通过优化工艺参数,比较刻蚀结果,最终获得了适合于刻蚀CCD小孔的工艺条件。     

碲镉汞器件接触孔的ICP刻蚀工艺研究

介绍了ICP等离子体刻蚀技术的工作原理和主要工艺参数,阐述了碲镉汞器件接触孔ICP刻蚀工艺的特点和技术要求。通过一系列实验和分析,最终优化并确定了ICP刻蚀碲镉汞材料接触孔的工艺参数,获得了良好的刻蚀形貌和器件性能。     

Characterization of surface channel CCD image arrays at low light levels

The characterization of surface channel charge-coupled device line imagers with front-surface imaging, interline transfer, and 2-phase stepped oxide, silicon-gate CCD registers is presented. The analysis, design, and evaluation of 1/spl times/64 CCD line arrays are described in terms of their performance at low light levels. The authors describe the responsivity, resolution, spectral, and noise measurements on silicon-gate CCD sensors and CCD interline shift-registers. The influence of transfer inefficiency and electrical fat-zero insertion on resolution and noise is described at low light levels.     

行间转移CCD的时间延迟积分调光方法

针对航空航天相机工作时由于曝光时间导致的图像质量下降问题,提出了行间转移面阵CCD的时间延迟积分(TDI)调光方法。选择行间转移面阵CCD KAI-16000作为成像器件,设计并完成了成像系统,利用FP-GA控制行间转移面阵CCD的驱动信号模式,将普通电子快门调光方法与TDI调光方法相结合,完成实时调光。实验结果表明:该成像系统无需延长曝光时间,依靠改变TDI工作模式下积分级数,解决了由于曝光时间不足导致的图像质量下降问题,图像信噪比(SNR)从13.22dB增加到33.74dB。     

A new CCD architecture of high-resolution and sensitivity for colordigital still picture

A new charged-coupled device (CCD) architecture developed for building high-resolution and high-sensitivity image sensors suitable for color digital still picture applications is presented. The sensor is based on the interline CCD structure. Both the interline pixels and the vertical charge transfer lines are utilized as light-sensing elements to improve simultaneously the resolution and sensitivity. This device is named the sea-of-photosensor array (SPA-CCD). A camera and supporting digital system were designed and built specifically to evaluate the device. Digital picture processing for white balance adjustment, chromatic correction, and high-frequency luminance was performed to improve color reproduction and picture resolution. An increased light sensitivity and limiting resolutions of 550 horizontal lines and 400 vertical lines on a TV screen were confirmed with an SPA-CCD of the same chip size as a conventional 190-k pixel IT-CCD. The new design of the SPA-CCD overcomes both the sensitivity and the resolution limitations of previous approaches     

A new configuration of CCD imager with a very low smear level—FIT-CCD imager

A new configuration of CCD imager has been developed to improve smearing. This new sensor introduces a storage region, which consists of pairs of vertical BCCD registers, between an interline transfer CCD imaging region and a readout horizontal CCD register. The configuration and operation of the new device (FIT-CCD imaging device) are described, together with the experimental results for 402(H) times 500(V) element imaging devices. The smear level observed is low as ∼0.45 percent at 50 times the saturation exposure, being the lowest level so far obtained in solid-state imagers. Degradation in the contrast transfer function due to introduction of the storage region is very little because of the minimized vertical transfer loss by the storage region configuration with pairs of half-long BCCD registers.     

A photoelectric conversion-characteristic control method for interline transfer CCD imager

There are generally two approaches to dynamic range expansion for a solid-state imager. One is output-noise decrease. Another approach is a maximum signal-charge increase. An interline transfer CCD imager has an advantage in regard to low output noise, while its maximum amount of signal charges is lower than that for the other kinds of imagers, MOS, CPD, etc. Using a new operation mode, dynamic-range expansion for the interline transfer CCD imager has been achieved. There is a knee point in the photoelectric conversion characteristic.     

基于FPGA的面阵CCD驱动电路设计

选用Kodak公司生产的大面阵行间转移型CCD（电荷耦合器件）芯片KAI-2093作为数码摄像机的图像传感器,介绍了其内部结构和工作原理,探讨了基于可编程逻辑器件FPGA用于对CCD驱动电路设计的方法和实现途径。基于KAI-2093的驱动时序和VHDL语言,给出了部分驱动时序的程序。结果表明本设计各项参数及指标均符合实际工作需要。此方法也可适用于其他类型的CCD驱动电路的设计。     

A 1920(H)×1035(V) pixel high-definition CCD image sensor

A 1920(H)×1035(V)-pixel high-definition CCD (charge-coupled-device) image sensor compatible with an 1125-scanning-lines and 16:9 aspect-ratio television system is described. The device basically uses an interline scheme with a vertical overflow drain. To maintain 74.25-MHz ultrahigh-data-rate operation, the device adopts a dual-channel configuration for the horizontal CCD (H-CCD) register. To accomplish both vertical signal charge transfer in the vertical CCD (V-CCD) register and signal charge distribution from the V-CCD registers into the dual-channel horizontal CCD registers simultaneously within a 3.77-μs short horizontal blanking period, a one-horizontal-period signal storage memory electrode and optical black memory are introduced. Bipolar buffer transistor chips are hybridized in the same package as the device, so as to reduce parasitic capacitance at CCD output terminals and maintain a wide-bandwidth operation. The device operates successfully and 1000-TV-line limiting resolution was obtained for both vertical and horizontal directions. Total random noise was evaluated to be 41 electrons. Dynamic range reached 66 dB. Signal-to-noise ratio for a black/white (B/W) camera was 51.5 dB under F4.0 and 2000-lux illumination conditions