Timing modeling of latch-controlled sub-systems

We present a new timing model for latch-controlled sub-systems, referred to as the advanced black box model. The proposed model considers the transparency characteristics of latches in modeling and uses only the constraints on input signals and the characteristics of output departure time to represent the timing characteristics of the latch-controlled sub-system. Thus, it can be used for the efficient timing verification of the IP-based SoC design without re-verifying the internal timings of pre-verified Intellectual Properties (IPs) at the lower level. We also present an efficient algorithm to characterize the proposed model, which enables us to perform the timing characterization and verification of the given system simultaneously. The worst-case complexity of the entire characterization process is O(P×N²), where P and N are the numbers of primary inputs and latches in the system.     

Utilizing interdependent timing constraints to enhance robustness in synchronous circuits

Interdependent setup-hold times are exploited during the design process to improve the robustness of a circuit. Considering this interdependence only during static timing analysis (STA), as demonstrated in the previous work, is insufficient to fully exploit the capabilities offered by interdependence. This result is due to the strong dependence of STA results on the specific circuit, cell library, and operating frequency. Interdependence is evaluated in this paper for several technologies to determine the overall reduction in delay uncertainty rather than improvements in STA. Reducing delay uncertainty produces a more robust synchronous circuit. The increasing efficacy of interdependence in deeply scaled technologies is also demonstrated by investigating the effect of technology scaling on interdependent timing constraints.     

深亚微米ASIC设计中的时序约束与静态时序分析

在现代深亚微米专用集成电路(ASIC)设计流程中,为使电路性能达到设计者的预期目标,并满足电路工作环境的要求,必须对一个电路设计进行诸如时序、面积、负载等多方面的约束,并自始至终使用这些约束条件来驱动电路设计软件的工作.文中介绍了设计中所需考虑的各种时序约束,并以同步数字系列(SDH)传输系统中8路VC12-VC4 E1映射电路设计为例,详细说明了设计中所采用的时序约束,并通过静态时序分析(STA)方法使电路时序收敛得到了很好的验证.     

A survey on estimating the timing constraints of hard real-time systems

A real-time computer system must interact with its environment in terms that are dictated by the occurrence of a significant event or simply by the passage of time. The computational activities triggered by these stimuli are expected to provide the correct results at the right time, since a real-time controller must meet the timing constraints that are dictated by its particular environment. If a computer controller fails to meet these time constraints, the controlled system may suffer a behavioural degradation from where, in some cases, a catastrophe can emerge. Thus, the correct estimation and handling of the timing constraints of a controlled system are central issues for the specification, development and test of a real-time computer controller, in a job that requires the scientific contribution of system engineers and real-time computer designers.In this paper we survey proposed solutions and concepts for estimating the timing constraints and the behavioural degradation of a controlled system when it suffers the impact of a timing failure. Although it is universally agreed that these are central issues for the development of predictable real-time controllers, this study shows that, except for a few cases, current literature does not place on them as much emphasis as one could expect. Moreover, a systematic method for evaluating the timing constraints of a controlled system does not seem to actually exist.     

A microwave injection-locking technique for direct timingextraction in multi-Gbit/s fiber optic data links

Direct timing extraction up to 5.8 GHz in a modified-Manchester-coded time-division multiplexed (TDM) fiber-optic transmission system is reported. The presence of an enhanced discrete timing component surrounded by depressed continuous components in the spectra of the received data is demonstrated experimentally and is supported by theory. The enhanced discrete component is used to injection-lock an electronic oscillator, thus directly generating a large timing signal. The technique is suitable for direct optical injection-locking for timing extraction     

VTP-CSMA: A Virtual Token Passing Approach for Real-Time Communication in IEEE 802.11 Wireless Networks

Currently, there is a trend towards the implementation of industrial communication systems using wireless networks. However, keeping up with the timing constraints of real-time traffic in wireless environments is a hard task. The main reason is that real-time devices must share the same communication medium with timing unconstrained devices. The VTP-CSMA architecture has been proposed to deal with this problem. It considers an unified wireless system in one frequency band, where the communication bandwidth is shared by real-time and non-real-time communicating devices. The proposed architecture is based on a virtual token passing (VTP) procedure that circulates a virtual token among real-time devices. This virtual token is complemented by an underlying traffic separation mechanism that prioritizes the real-time traffic over the non-real-time traffic. This is one of the most innovative aspects of the proposed architecture, as most part of real-time communication approaches are not able to handle timing unconstrained traffic sharing the same communication medium. A ring management procedure for the VTP-CSMA architecture is also proposed, allowing real-time stations to adequately join/leave the virtual ring.     

Min-max timing analysis and an application to asynchronous circuits

Modern high-performance asynchronous circuits depend on timing constraints for correct operation, so timing analyzers are essential asynchronous design tools. In this paper we present a 13-valued abstract waveform algebra and a polynomial-time min-max timing simulation algorithm for use in efficient, approximate timing analysis of asynchronous circuits with bounded component delays. Unlike several previous approaches, our algorithm computes separate propagation delay bounds from each circuit input to each internal gate. This is useful for analyzing asynchronous circuits, where the relative transition times of the inputs may not be known a priori, unlike synchronous circuits. We also describe an efficient reconvergent fanout analysis technique that helps in increasing the accuracy of simulation. We have applied our algorithm to build an efficient timing analysis tool for extended burst-mode circuits (a class of timing-dependent asynchronous circuits) implemented in the 30 design style. Our tool analyzes gate-level 30 circuits assuming bounded component delays and determines safe timing constraints for correct operation. Although our results represent conservative approximations to the true timing requirements in the worst case, experiments indicate that our technique is efficient and fairly accurate in practice     

一种数据辅助的前向位定时估计算法

以平方法为代表的非数据辅助(NDA)类前向位定时估计算法在低信噪比和小成性系数场合估计性能严重恶化,而采用数据辅助(DA)类估计是值得考虑的选择。但传统的数据辅助类算法需要大量的搜索以获取位定时的精确估计,运算量大实现困难。本文将三角内插技术应用于位定时估计,提出了一种新的数据辅助前向位定时估计算法,该算法简单、便于实现。仿真结果表明,本文算法估计性能逼近修正卡美罗界(MCRB),且对成形滚降系数不敏感,适合于低信噪比突发通信。最后,本文针对突发信号给出了前导码捕获与位定时估计一体化的实现结构。      

一种降低电路泄漏功耗的多阈值电压方法

目前,多阈值电压方法是缓解电路泄漏功耗的有效手段之一。但是,该方法会加重负偏置温度不稳定性(NBTI)效应,导致老化效应加剧,引起时序违规。通过找到电路的潜在关键路径集合,运用协同优化算法,将关键路径集合上的门替换为低阈值电压类型,实现了一种考虑功耗约束的多阈值电压方法。基于45 nm工艺模型及ISCAS85基准电路的仿真结果表明,在一定功耗约束下,该方法的时延改善率最高可达12.97%,明显优于常规多阈值电压方法。电路的规模越大,抗泄漏功耗的效果越好。     

Synthesis Scheme for Low Power Designs Under Timing Constraints

To minimize the power consumption with resources operating at multiple voltages a timeconstrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The timeconstrained algorithm has time complexity of Ｏ（ｎ２）,where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46.5%.     

On real-time databases: concurrency control and scheduling

In addition to maintaining database consistency as in conventional databases, real-time database systems must also handle transactions with timing constraints. While transaction response time and throughput are usually used to measure a conventional database system, the percentage of transactions satisfying the deadlines or a time-critical value function is often used to evaluate a real-time database system. Scheduling real-time transactions is far more complex than traditional real-time scheduling in the sense that (1) worst case execution times are typically hard to estimate, since not only CPU but also I/O requirement is involved; and (2) certain aspects of concurrency control may not integrate well with real-time scheduling. In this paper, we first develop a taxonomy of the underlying design space of concurrency control including the various techniques for achieving serializability and improving performance. This taxonomy provides us with a foundation for addressing the real-time issues. We then consider the integration of concurrency control with real-time requirements. The implications of using run policies to better utilize real-time scheduling in a database environment are examined. Finally, as timing constraints may be more important than data consistency in certain hard realtime database applications, we also discuss several approaches that explore the nonserializable semantics of real-time transactions to meet the hard deadlines     

一种基于时间限制条件的低功耗高层综合设计方案

提出了多电压时间限制下电路功耗最小的高层综合设计算法,其输入为数据流图及时间限制条件.由于多电压设计会引起低层布局时的连线复杂性提高,所以提出的算法在进行高层调度过程同时考虑了低层分区问题,即算法利用调度步骤降低功耗,利用分区步骤来减小连线的复杂性.该算法的时间复杂性为O(n2),n是DFG图中的结点个数.大量的DSP基准实验表明该算法使得电路功耗平均降低46.5%.     

Timing Synchronization for Cooperative Communications with Detect and Forward Relaying

A non-data-aided near maximum likelihood (NDA-NML) symbol timing estimator is presented, which is applied to a cooperative communication system with a source, relay and destination. A Cramer rao bound (CRB) for the estimator for asymptotically low signal-to-noise (SNR) ratio case is derived. The timing complexity of the NDA-NML estimator is derived and compared with the correlation based data-aided maximum likelihood (DA-ML) estimator. It is demonstrated that the complexity of the NDA-NML estimator is much less than that of correlation based DA-ML estimator. The bit-error-rate (BER) performance of this system operating in a detect-and-forward (DAF) mode is studied where the channel state information (CSI) is available at the receiver and the symbol timings are estimated independently for each channel. SNR combining (SNRC) and equal ratio combining (ERC) methods are considered. It is found that timing estimation error has a significant effect on BER performance. It is also found that for large timing error the benefit of cooperative diversity could vanish. It is demonstrated that significant gains can be made with both combining methods with cooperation and timing estimation, where the gains are the same for both estimators.     

A scheduling scheme with Dynamic Frequency Clocking and multiple voltages for low power designs

In this letter, a scheduling scheme based on Dynamic Frequency Clocking （DFC） and multiple voltages is proposed for low power designs under the timing and the resource constraints. Unlike the conventional methods at high level synthesis where only voltages of nodes were considered, the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.     

Code timing acquisition for DS-CDMA in fading channels bydifferential correlations

We propose simple and efficient algorithms for the code timing acquisition in the direct-sequence code-division multiple-access communication system. The essential assumption is that a preamble or an unmodulated pilot channel is available for the desired user. Then the correlation matrix R(τ) of the sampled data, where τ is suitably chosen time lag, contains the timing information only of desired user, while the contributions of uncorrelated interferers and noise are suppressed out. Hence, compared to the conventional approach, more interference suppression is achieved. Coarse delay estimates are then obtained by a matched filter (MF) or multiple signal classification-type approaches. In the latter case, only L eigenvectors are computed, where L is the number of resolvable paths. If only one path exists, an additional procedure is proposed to both approaches, by which the estimation accuracy is greatly improved with negligible increase in computation. More precisely, the chip timing offset due to chip-asynchronous sampling can be determined by solving a system of two second-order polynomials for each chip interval. Therefore, only at most 2C hypotheses are needed, where C is the processing gain. All the proposed methods are computationally quite simple, containing mainly MF-operations, or at most computation of only few eigenvectors. Mean acquisition time analysis is carried out semi-analytically. Numerical experiments speaks for the possibility of achieving significant performance gains compared to conventional acquisition, especially in the presence of strong multiple-access interference, making them attractive options to be attached for the next generation mobile receivers     

A Maximum Likelihood Receiver for an Orthogonally Multiplexed QAM System

A maximum likelihood receiver for an orthogonally multiplexed QAM (OQAM) system has been derived based on the mathematical structure of an OQAM signal. The resulting receiver provides the minimum variance estimates of carrier and timing phases under the disturbance caused by not only Gaussian noise but also random data. It has also been proven that the carrier and timing joint control system is asymptotically stable almost everywhere in a state space. The equilibrium points are where the parallel synchronization over all subchannels in the OQAM system is established. Simulations have been carried out in order to verify the maximum likelihood receiver performances, where 9600 bit/s data are transmitted over 750-2450 Hz voiceband with 8×8 staggered QAM signal constellations. It has been shown that sufficient eye opening is obtained under 10 Hz carrier frequency offset and 10^-4timing frequency stability.     

Synthesis of timed asynchronous circuits

The authors present a systematic procedure for synthesizing timed asynchronous circuits using timing constraints dictated by system integration, thereby facilitating natural interaction between synchronous and asynchronous circuits. Their timed circuits also tend to be more efficient, in both speed and area, compared with traditional asynchronous circuits. The synthesis procedure begins with a cyclic graph specification to which timing constraints can be added. First, the cyclic graph is unfolded into an infinite acyclic graph. Then, an analysis of two finite subgraphs of the infinite acyclic graph detects and removes redundancy in the original specification based on the given timing constraints. From this reduced specification, an implementation that is guaranteed to function correctly under the timing constraints is systematically synthesized. With practical circuit examples, it is demonstrated that the resulting timed implementation is significantly reduced in complexity compared with implementations previously derived using other methodologies     

Symbol Timing Recovery for CPM with Correlated Data Symbols

We consider symbol timing recovery for continuous phase modulations (CPMs) with correlated data symbols. A popular example of such a scheme is shaped offset quadrature phase-shift keying (SOQPSK). We propose an extension to an existing non-data-aided (blind) timing error detector (TED) to make it compatible with such modulation schemes. The merits of the modified TED are demonstrated by comparing its performance with and without taking the data correlation into account. As a further modification, we show that a quantization scheme can be used to yield an extremely low-complexity version of the system with only negligible performance losses. The Scurve of the proposed quantized TED is given, which rules out the existence of false lock points. The proposed scheme shows great promise in a wide range of applications due to its low complexity, its lack of false lock points, and its blind nature; such applications include timing recovery for noncoherent detection schemes and false lock detectors.