An ultralow-power switched opamp-based 10-B integrated ADC for implantable biomedical applications

This paper describes an ultralow-power switched opamp-based integrated analog-to-digital converter (ADC) for cardiac pacemakers applications. The ADC consumption, measured on 10 chip samples and averaged, is 8.18 /spl mu/W (stand-by value: 1 nW) for the analog part and of 9.71 /spl mu/W (5 nW) for the digital one, using a supply battery of 2.8 V. The converter has a resolution of 10-b, its typical operating clock frequency is 32 KHz (2.9 KS/s sampling rate) and is able to reach the same resolution at 2 V (0.7 KS/s sampling rate), with a dissipation of 1 /spl mu/W and 1.3 /spl mu/W for analog and digital part, respectively.     

A low-power 22-bit incremental ADC

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 /spl mu/V/sub RMS/), the DC offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 /spl mu/A current during conversion.     

A time-to-digital-converter-based CMOS smart temperature sensor

A time-to-digital-converter-based CMOS smart temperature sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on voltage/current ADCs for digital output code conversion. For the purpose of cost reduction and power savings, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter is utilized to convert the pulse into a corresponding digital code. The test chips have an extremely small area of 0.175 mm/sup 2/ and were fabricated in the TSMC CMOS 0.35-/spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.7/spl sim/+0.9/spl deg/C after two point calibration, but without any curvature correction or dynamic offset cancellation. The effective resolution is better than 0.16/spl deg/C, and the power consumption is under 10 /spl mu/W at a sample rate of 2 samples/s.     

A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/spl mu/m CMOS

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-/spl mu/m CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The /spl Sigma//spl Delta/ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

A 0.5-V 1-/spl mu/W successive approximation ADC

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.     

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.     

A self-calibrating 15 bit CMOS A/D converter

A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.     

A high-speed NMOS A/D converter with a current source array

A high-speed MOS analog-to-digital (A/D) converter has been designed and fabricated in a standard single channel metal-gate enhancement/depletion MOS process. The use of current switching performs a conversion time of 13.2 /spl mu/s at a resolution of 8 bits. To replace the resistance ladder a binary weighted current source array has been implemented which consists of MOS transistors. The test circuit requires 4 mm/SUP 2/ including all analog circuit functions without the successive approximation register.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.     

A new successive approximation architecture for low-power low-cost CMOS A/D converter

A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm/sup 2/ with the TSMC 0.35-/spl mu/m single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.     

A baseband processor for impulse ultra-wideband communications

This paper presents a baseband processor architecture for pulsed ultra-wideband signals. It consists of an analog-to-digital converter (ADC), a clock generation system, and a digital back-end. The clock generation system provides different phases of a 300-MHz clock using four differential inverter stages. The specification of the jitter standard deviation is 100 ps. The Flash interleaved ADC provides four bit samples at 1.2 Gsps. The back-end uses parallelization to process these samples and to reduce the signal acquisition time to 65 /spl mu/s. The entire synchronization algorithm is implemented in the digital domain, without feeding any signals back to the clock control. The baseband processor and ADC were implemented on the same 0.18-/spl mu/m CMOS die at 1.8 V as part of a complete baseband transceiver. A wireless data rate of 193 kb/s is demonstrated.     

An analog front end for 2400-bit/s split-band full-duplex modems

An analog front-end LSI for 1200/2400 full-duplex modems which conform to CCITT V.22. and Bell 212A is described. The chip includes A/D and D/A converters, bandlimiting filters, delay equalizers, AGC circuit, tone generator, multipurpose low-pass filter, and voltage reference generator. The chip is fabricated by a 5-/spl mu/m CMOS process, and chip size is 6.50 mm/spl times/6.37 mm. The circuit operates from +5.0-V and -5.0-V power supplies. Typical power consumption is 100 mW.     

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.     

A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio

An audio /spl Sigma//spl Delta/ analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-/spl mu/m CMOS process, and achieves 106-dB dynamic range, -99-dB THD+N.     

A digital pixel sensor array with programmable dynamic range

This paper presents a digital pixel sensor (DPS) array employing a time domain analogue-to-digital conversion (ADC) technique featuring adaptive dynamic range and programmable pixel response. The digital pixel comprises a photodiode, a voltage comparator, and an 8-bit static memory. The conversion characteristics of the ADC are determined by an array-based digital control circuit, which linearizes the pixel response, and sets the conversion range. The ADC response is adapted to different lighting conditions by setting a single clock frequency. Dynamic range compression was also experimentally demonstrated. This clearly shows the potential of the proposed technique in overcoming the limited dynamic range typically imposed by the number of bits in a DPS. A 64 /spl times/ 64 pixel array prototype was manufactured in a 0.35-/spl mu/m, five-metal, single poly, CMOS process. Measurement results indicate a 100 dB dynamic range, a 41-s mean dark time and an average current of 1.6 /spl mu/A per DPS.     

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-/spl mu/m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8/spl times/3.6 mm/sup 2/, and the power consumption is 370 mW with a single 2.5-V supply.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

High-resolution A/D conversion in MOS/LSI

A new successive approximation analog-to-digital conversion technique compatible with most MOS process technologies is described. This technique combines a string of equal value diffused resistors and a binary ratioed capacitor array in a unique circuit configuration so that 12-bit monotonicity is achieved with only 8-bit ratio-accurate circuit elements. The comparator is realized by a chopper-stabilized amplifier to reduce the inherently high input offset voltages of MOS amplifiers. Typical performance characteristics taken from a sample of ICs are presented; 12-bit monotonic conversion with differential nonlinearity less than 1/2 LSB is completed in 50 /spl mu/s. The die area, less logic, is 12000 mil/SUP 2/. Because of assured 12-bit monotonicity, this converter should find applications of closed-loop control systems. It seems feasible to extend this technique to 14-bit resolution for use in applications such as digital audio systems.