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一种适合制作CMOS的SiGePMOSFET 总被引:1,自引:1,他引:0
在通常适合于制作埋沟 Si Ge NMOSFET的 Si/弛豫 Si Ge/应变 Si/弛豫 Si Ge缓冲层 /渐变 Ge组分层的结构上 ,制作成功了 Si Ge PMOSFET.这种 Si Ge PMOSFET将更容易与 Si Ge NMOSFET集成 ,用于实现 Si Ge CMOS.实验测得这种结构的 Si Ge PMOSFET在栅压为 3.5 V时最大饱和跨导比用作对照的 Si PMOS提高约 2倍 ,而与常规的应变 Si Ge沟道的器件相当 相似文献
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为研究深亚微米尺度下应变 Si Ge沟改进 PMOSFET器件性能的有效性 ,运用二维数值模拟程序MEDICI模拟和分析了 0 .1 8μm有效沟长 Si Ge PMOS及 Si PMOS器件特性。Si Ge PMOS垂直方向采用 Si/Si Ge/Si结构 ,横向结构同常规 PMOS,N+ -poly栅结合 P型δ掺杂层获得了合理阈值电压及空穴局域化。研究表明 ,经适当设计的 Si Ge PMOS比对应 Si PMOS的 IDmax、gm、f T均提高 1 0 0 %以上 ,表明深亚微米尺度 Si Ge沟PMOSFET具有很大的性能提高潜力 相似文献
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本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成. 相似文献
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在考虑应变对SiGe合金能带结构参数影响的基础上,建立了一个半经验的Si1-xGexpMOSFET反型沟道空穴迁移率模型。该模型重点讨论了反型电荷对离化杂质散射的屏蔽作用,由此对等效体晶格散射迁移率进行了修正。并且详细讨论了等效体晶格散射迁移率随掺杂浓度Nd和组分x的变化。利用该模型,对影响空穴迁移率的主要因素进行了分析讨论。通过模拟得出,增加组分x可以显著提高等效体晶格散射迁移率,从而可以提高PMOSFET的空穴迁移率。 相似文献
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对绝缘层上Si/应变Si1-xGex/Si异质结p-MOSFET电学特性进行二维数值分析,研究了该器件的阈值电压特性、转移特性、输出特性.模拟结果表明,随着应变Si1-xGex沟道层中的Ge组分增大,器件的阈值电压向正方向偏移,转移特性增强;当偏置条件一定时,漏源电流的增长幅度随着Ge组分的增大而减小;器件的输出特性呈现出较为明显的扭结现象. 相似文献
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为充分利用应变 Si Ge材料相对于 Si较高的空穴迁移率 ,研究了 Si/Si Ge/Si PMOSFET中垂直结构和参数同沟道开启及空穴分布之间的依赖关系。在理论分析的基础上 ,以数值模拟为手段 ,研究了栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分及厚度、缓冲层厚度及衬底掺杂浓度对阈值电压、交越电压和空穴分布的影响与作用 ,特别强调了 δ掺杂的意义。模拟和分析表明 ,栅氧化层厚度、Si帽层厚度、Si Ge层 Ge组分、衬底掺杂浓度及 δ掺杂剂量是决定空穴分布的主要因素 ,而 Si Ge层厚度、缓冲层厚度和隔离层厚度对空穴分布并不敏感。最后总结了沟道反型及空穴分布随垂直结构及参数变化的一般规律 ,为优化器件设计提供了参考。 相似文献
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首先建立了应变SiGe沟道PMOSFET的一维阈值电压模型,在此基础上,通过考虑沟道横向电场的影响,将其扩展到适用于短沟道的准二维阈值电压模型,与二维数值模拟结果呈现出好的符合。利用此模型,模拟分析了各结构参数对器件阈值电压的影响,并简要讨论了无Sicap层器件的阈值电压。 相似文献
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Ding-Lei Mei Jing-chun Li Jing Zhang Wan-jing Xu Kai-zhou Tan Mo-hua Yang 《Microelectronics Journal》2004,35(12):969-971
A novel MBE-grown method using low-temperature Si technology is introduced into the fabrication of strained Si channel PMOSFETs. The thickness of relaxed Si1−xGex epitaxy layer on bulk silicon is reduced to approximate 400 nm (x=0.2). The Ge fraction and relaxation of Si1−xGex film are confirmed by DCXRD (double crystal X-ray diffraction) and the DC characteristics of strined Si channel PMOSFET measured by HP 4155B indicate that hole mobility μp has an maximum enhancement of 25% compared to similarly processed bulk Si PMOSFET. 相似文献
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High-mobility strained-Si PMOSFET's 总被引:1,自引:0,他引:1
Nayak D.K. Goto K. Yutani A. Murota J. Shiraki Y. 《Electron Devices, IEEE Transactions on》1996,43(10):1709-1716
Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si0.82Ge0.18 buffer layer on Si(100) substrate. At high vertical fields (high |Vg|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO2 interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K 相似文献
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By employing the semiconductor device 2D simulator Medici, the inversion layer quantum mechanics effects (QME) in the strained SiGe-channel PMOSFET are studied. The influences of the inversion layer QME on the channel hole sheet density, the surface potential, the electric field and the threshold voltage in strained SiGe PMOS and Si PMOS are simulated and compared. It is theoretically predicted and validated by the numeric simulation results that QME lead to much difference in device performance between SiGe PMOS and Si PMOS. This study shows that SiGe PMOS suffers less disadvantageous influence when compared with Si PMOS, in ultra-deep submicron dimension, where QME are becoming increasingly more important. 相似文献
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Si/SiGe P-channel Metal-Oxide-Semiconductor Field Effect Transistor (PMOSFET) using P^+ (phosphor ion) implantation technology is successfully fabricated. P^+ implantation into SiGe virtual substrate induces a narrow defect region slightly below the SiGe/Si interface, which gives rise to strongly enhanced strain relaxation of SiGe virtual substrate. X-Ray Diffraction (XRD) tests show that the degree of relaxation of SiGe layer is 96% while 85% before implantation. After annealed, the sample appeared free of Threading Dislocation densities (TDs) within the SiGe layer to the limit of Transmission Electron Microscopy (TEM) analysis. Atomic Force Microscope (AFM) test of strained Si channel surface shows that Root Mean Square (RMS) is 1.1nm. The Direct Current (DC) characters measured by HP 4155B indicate that the maximum saturated transconductance is twice bigger than that of bulk Si PMOSFET. 相似文献
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本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。 相似文献
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The application of molecular layer doping (MLD) to the formation of shallow source and drain regions of a PMOSFET is discussed. The MLD process consists of three steps. First, the natural oxide on the Si surface is removed by thermal cleaning to expose an active Si surface. Second, a boron adsorbed layer is formed on the Si surface. Third, boron atoms undergo solid-phase diffusion from the adsorbed layer into the bulk. The electrical characteristics of the PMOSFET in the short-channel region are superior to those of devices fabricated by conventional techniques 相似文献