双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

p+多晶Si1-xGex功函数对异质结CMOS器件电学特性影响的模拟研究

为使垂直层叠SiGe/Si异质结CMOS器件具有匹配的阈值电压,利用二维器件模拟器MEDICI模拟分析了p 多晶Si1-xGex栅的功函数对此类器件直流与交流特性参数的影响,得出在P 多晶Si1-xGex功函数W=0.85 eV,即Ge组分x=0.36时,此类器件的p-MOSFET与n-MOSFET具有匹配的阈值电压,分别为VTp=-0.215 V和VTn=O.205 V.为此类器件的优化设计和制备提供了理论依据.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

应变SiGe沟道PMOSFET亚阈值特性模拟

通过简化的模型,对应变SiGe沟道PMOSFET及Si PMOSFET的亚阈值特性作出了简单的理论分析,然后用二维模拟器Medici进行了模拟和对比;研究了截止电流和亚阈值斜率随SiGe PMOSFET垂直结构参数的变化关系。模拟结果同理论分析符合一致,表明应变SiGe沟道PMOSFET的亚阈值特性比Si PMOSFET更差,并且对垂直结构参数敏感,在器件设计时值得关注。     

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

双栅双应变沟道全耗尽SOI CMOS的瞬态特性分析

在提出双栅双应变沟道全耗尽SOl MOSFET新结构的基础上,模拟了沟道长度为25nm时基于新结构的CMOS瞬态特性.结果表明,单栅工作模式下,传统应变SiGe(或应变Si)器件的CMOS电路只能实现上升(或下降)时间的改善,而基于新结构的CMOS电路能同时实现上升和下降时间的缩短;双栅模式下,CMOS电路的上升和下降时间较单栅模式有了更进一步的改善,电路性能得以显著提高.     

一种适合制作CMOS的SiGe PMOSFET

在通常适合于制作埋沟SiGe NMOSFET的Si/弛豫SiGe/应变Si/弛豫SiGe缓冲层/渐变Ge组分层的结构上,制作成功了SiGe PMOSFET.这种SiGe PMOSFET将更容易与SiGe NMOSFET集成,用于实现SiGe CMOS.实验测得这种结构的SiGe PMOSFET在栅压为3.5V时最大饱和跨导比用作对照的Si PMOS提高约2倍,而与常规的应变SiGe沟道的器件相当.     

绝缘层上应变SiGe沟道p-MOSFET电学特性模拟分析

利用数值模拟软件ISE TCAD对绝缘层上应变SiGe(SGOI)和Si(SOI)p-MOSFET的电学特性进行了二维数值模拟.计算结果表明,与传统的SOI p-MOSFET相比,SGOI p-MOSFET的漏源饱和电流几乎要高出两倍; 其亚阈值电流要高出1～3个数量级.Ge合金组分作为应变SiGe沟道MOSFET的重要参数,就不同Ge合金组分对SGOI p-MOSFET的电学特性的影响也进行了较为深入的研究.随着Ge合金组分的增大,SGOI p-MOSFET的总体电学性能有所提高.     

绝缘层上Si/应变Si1-xGex/Si异质结p-MOSFET电学特性二维数值分析

对绝缘层上Si/应变Si1-xGex/Si异质结p-MOSFET电学特性进行二维数值分析,研究了该器件的阈值电压特性、转移特性、输出特性.模拟结果表明,随着应变Si1-xGex沟道层中的Ge组分增大,器件的阈值电压向正方向偏移,转移特性增强;当偏置条件一定时,漏源电流的增长幅度随着Ge组分的增大而减小;器件的输出特性呈现出较为明显的扭结现象.     

A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (/spl epsiv//spl sim/ -1.07%) strained- Si/sub 0.55/Ge/sub 0.45/ and the n-MOSFET in tensile-strained Si over the relaxed Si/sub 0.80/Ge/sub 0.20/ exhibited significant hole (enhancement factor /spl sim/ 1.9) and electron (enhancement factor /spl sim/ 1.6) mobility enhancements over the Si reference.     

Ultrathin body SiGe-on-insulator pMOSFETs with high-mobility SiGe surface channels

A novel concept and a fabrication technique of strained SiGe-on-insulator (SGOI) pMOSFET are proposed and demonstrated. This device has an ultrathin strained SiGe channel layer, which is directly sandwiched by gate oxide and buried oxide layers. The mobility enhancement of 2.3 times higher than the universal mobility of conventional universal Si pMOSFETs was obtained for a pMOSFET with 19-nm-thick Si/sub 0.58/Ge/sub 0.42/ channel layer, which is formed by high-temperature oxidation of a Si/sub 0.9/Ge/sub 0.1/ layer grown on a Si-on-insulator (SOI) substrate. A fully depleted SGOI MOSFET with this simple single-layer body structure is promising for scaled SOI p-MOSFET with high current drive.     

Strained‐SiGe Complementary MOSFETs Adopting Different Thicknesses of Silicon Cap Layers for Low Power and High Performance Applications

We introduce a strained‐SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si‐cap layers in n‐channel and p‐channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high‐electron‐mobility Si surface channel in nMOSFETs and a compressively strained high‐hole‐mobility Si_0.8Ge_0.2 buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate‐leakage levels. Unlike the conventional strained‐Si CMOS employing a relatively thick (typically > 2 µm) Si_xGe_1‐x relaxed buffer layer, the strained‐SiGe CMOS with a very thin (20 nm) Si_0.8Ge_0.2 layer in this study showed a negligible self‐heating problem. Consequently, the proposed strained‐SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.     

Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiOx/TiSiN gate stacks

The self-gain of surface channel compressively strained SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks is investigated for a range of gate lengths down to 55 nm. There is 125% and 700% enhancement in the self-gain of SiGe pMOSFETs compared with the Si control at 100 nm and 55 nm lithographic gate lengths, respectively. This improvement in the self-gain of the SiGe devices is due to 80% hole mobility enhancement compared with the Si control and improved electrostatic integrity in the SiGe devices due to less boron diffusion into the channel. At 55 nm gate length, the SiGe pMOSFETs show 50% less drain induced barrier lowering compared with the Si control devices. Electrical measurements show that the SiGe devices have larger effective channel lengths. It is shown that the enhancement in the self-gain of the SiGe devices compared with the Si control increases as the gate length is reduced thereby making SiGe pMOSFETs with HfSiO_x/TiSiN gate stacks an excellent candidate for analog/mixed-signal applications.     

P型张应变Si/SiGe量子阱红外探测器的能带设计

提出P型张应变Si/SiGe量子阱红外探测器(QWIP)结构,应用k·P方法计算应变Si/SiGe量子阱价带能带结构和应变SiGe合金空穴有效质量.结果表明量子阱中引入张应变使轻重空穴反转,基态为有效质量较小的轻空穴态,因此P型张应变Si/SiGe QWIP与n型QWIP相比具有更低的暗电流;而与P型压应变或无应变QWIP相比光吸收和载流子输运特性具有较好改善.在此基础上讨论了束缚态到准束缚态子带跃迁型张应变p-Si/SiGe QWIP的优化设计.     

Investigation of Coulomb scattering on sSi/Si0.5Ge0.5/sSOI quantum-well p-MOSFETs

sSi/Si_0.5Ge_0.5/sSOI quantum-well (QW) p-MOSFETs with HfO₂/TiN gate stack were fabricated and characterized. According to the low temperature experimental results, carrier mobility of the strained Si_0.5Ge_0.5 QW p-MOSFET was mainly governed by phonon scattering from 300 to 150 K and Coulomb scattering below 150 K, respectively. Coulomb scattering was intensified by the accumulated inversion charges in the Si cap layer of this Si/SiGe heterostructure, which led to a degradation of carrier mobility in the SiGe channel, especially at low temperature.     

用减压化学气相沉积技术制备应变硅材料

利用减压化学气相沉积技术，制备出应变Si/弛豫Si0.9Ge0.1/渐变组分弛豫SiGe/Si衬底. 通过控制组分渐变SiGe过渡层的组分梯度和适当优化弛豫SiGe层的外延生长工艺，有效地降低了表面粗糙度和位错密度.与Ge组分突变相比，采用线性渐变组分后，应变硅材料表面粗糙度从3.07nm减小到0.75nm，位错密度约为5E4cm-2，表面应变硅层应变度约为0.45%.