A Millimeter-Wave (40–45 GHz) 16-Element Phased-Array Transmitter in 0.18-$mu$ m SiGe BiCMOS Technology

This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications. The transmitter array is based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network. A 1:2 active divider and two 1:8 passive tee-junction dividers constitute the corporate-feed network, and three-dimensional shielded transmission-lines are used for the passive divider to minimize area. All signals are processed differentially inside the chip except for the input and output interfaces. The phased-array transmitter results in a 12.5 dB of average power gain per channel at 42.5 GHz with a 3-dB gain bandwidth of 39.9-45.6 GHz. The RMS gain variation is < 1.3 dB and the RMS phase variation is < for all 4-bit phase states at 35-50 GHz. The measured input and output return losses are < -10 dB at 36.6-50 GHz, and <-10 dB at 37.6-50 GHz, respectively. The measured peak-to-peak group delay variation is plusmn 20 ps at 40-45 GHz. The output P_-1dB is -5plusmn1.5 dBm and the maximum saturated output power is - 2.5plusmn1.5 dBm per channel at 42.5 GHz. The transmitter shows <1.8 dB of RMS gain mismatch and < 7deg of RMS phase mismatch between the 16 different channels over all phase states. A - 30 dB worst-case port-to-port coupling is measured between adjacent channels at 30-50 GHz, and the measured RMS gain and phase disturbances due to the inter-channel coupling are < 0.15 dB and < 1deg, respectively, at 35-50 GHz. All measurements are obtained without any on-chip calibration. The chip consumes 720 mA from a 5 V supply voltage and the chip size is 2.6times3.2 mm².     

A 43-Gb/s full-rate clock transmitter in 0.18-/spl mu/m SiGe BiCMOS technology

A 43-Gb/s full-rate clock transmitter chip for SONET OC-768 transmission systems is reported. The IC is implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120 GHz f/sub T/ and 100 GHz f/sub max/ HBTs. It consists of a 4:1 multiplexer, a clock multiplier unit, and a frequency lock detector. The IC features clock jitter generation of 260 fs rms and dissipates 2.3 W from a -3.6-V supply voltage. Measurement results are compared to a previously reported half-rate clock transmitter designed using the same technology.     

A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $mu$m SiGe BiCMOS Technology

This paper presents a 12 GHz direct digital synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm². The chip was measured in packaged prototypes using 48-pin ceramic LCC packages.     

Efficient breakdown voltage doubler for 10 Gbit/s SiGe modulator drivers

A novel intrinsic collector-base capacitance (C_CB) feedback network was incorporated into the series-connected voltage balancing (SCVB) circuit configuration to implement 10 Gbit/s SiGe modulator drivers. The driver fabricated in 0.35 mum SiGe BiCMOS process could output 9 V_PP differential output swing with rise/fall time (20 to 80%) less than 27 ps. Compared with drivers using only SCVB, the power consumption could be greatly reduced from 2 to 1 W     

165-GHz Transceiver in SiGe Technology

Two D-band transceivers, with and without amplifiers and static frequency divider, transmitting simultaneously in the 80-GHz and 160-GHz bands, are fabricated in SiGe HBT technology. The transceivers feature an 80-GHz quadrature Colpitts oscillator with differential outputs at 160 GHz, a double-balanced Gilbert-cell mixer, 170-GHz amplifiers and broadband 70-GHz to 180-GHz vertically stacked transformers for single-ended to differential conversion. For the transceiver with amplifiers and static frequency divider, which marks the highest level of integration above 100 GHz in silicon, the peak differential down-conversion gain is -3 dB for RF inputs at 165 GHz. The single-ended, 165-GHz transmitter output generates -3.5 dBm, while the 82.5-GHz differential output power is +2.5 dBm. This transceiver occupies 840 mum times 1365 mum, is biased from 3.3 V, and consumes 0.9 W. Two stand-alone 5-stage amplifiers, centered at 140 GHz and 170 GHz, were also fabricated showing 17 dB and 15 dB gain at 140 GHz and 170 GHz, respectively. The saturated output power of the amplifiers is +1 dBm at 130 GHz and 0 dBm at 165 GHz. All circuits were characterized over temperature up to 125degC. These results demonstrate for the first time the feasibility of SiGe BiCMOS technology for circuits in the 100-180-GHz range.     

一种6.25 Gb/s带预加重结构的低压差分发送器

采用SMIC 40 nm CMOS工艺,设计了一种带预加重结构的低压差分(LVDS)发送器。低压差分驱动器采用双运放反馈控制电路,可稳定输出信号的摆幅。采用边沿检测电流注入的预加重电路,对输出进行高频预加重,克服了数据高速传输中高频信号的损失。该发送器的速率为6.25 Gb/s,输出差分信号摆幅为300 mV,预加重比例为3.5 dB,功耗为7.1 mW。该低压差分发送器可应用于高速IO物理层电路中。     

A 10 Gb/s BiCMOS adaptive cable equalizer

A 10 Gb/s adaptive equalizer IC using SiGe BiCMOS technology is described. The circuit consists of the combination of an analog equalizer and an adaptive feedback loop for minimizing the inter-symbol interference (ISI) for a variety of cable characteristics. The adaptive loop functions using a novel slope-detection circuit which has a characteristic that correlates closely with the amount of ISI. The chip occupies an area of 0.87 mm/spl times/0.81 mm and consumes a power of 350 mW with 3.3 V power supply. This adaptive equalizer is able to compensate for a cable loss up to 22dB at 5 GHz while maintaining a low bit-error rate.     

A 0.18-/spl mu/m SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems

A 43-Gb/s receiver (Rx) and transmitter (Tx) chip set for SONET OC-768 transmission systems is reported. Both ICs are implemented in a 0.18-/spl mu/m SiGe BiCMOS technology featuring 120-GHz f/sub T/ and 100 GHz f/sub max/. The Rx includes a limiting amplifier, a half-rate clock and data recovery unit, a 1:4 demultiplexer, a frequency acquisition aid, and a frequency lock detector. Input sensitivity for a bit-error rate less than 10/sup -9/ is 40 mV and jitter generation better than 230 fs rms. The IC dissipates 2.4 W from a -3.6-V supply voltage. The Tx integrates a half-rate clock multiplier unit with a 4:1 multiplexer. Measured clock jitter generation is better than 170 fs rms. The IC consumes 2.3 W from a -3.6-V supply voltage.     

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$mu$m CMOS Technology

A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mV_pp differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.     

Wide Temperature Range Operation of a 1.55-$mu$m 40-Gb/s Electroabsorption Modulator Integrated DFB Laser for Very Short-Reach Applications

We present the uncooled operation of a 1.55- mum 40-Gb/s InGaAlAs electroabsorption modulator (EAM) integrated distributed-feedback (DFB) laser within a temperature range of 95degC (-15degC to 80degC ). To the best of our knowledge, this is the largest temperature range reported so far for such a 40-Gb/s EAM integrated DFB laser. We designed the EAM to operate at high speed by reducing the electrical parasitics, and we achieved a 3-dB frequency bandwidth of over 39 GHz for an EAM length of less than 150 mum. We demonstrated a 2-km single-mode fiber (SMF) transmission at 40-Gb/s over a wide temperature range of -15degC to 80degC by adjusting only the bias voltage to the EAM while keeping the modulation voltage swing constant at 2.0 V when the temperature changed. We achieved a dynamic extinction ratio of over 8.2 dB and a 2-km SMF transmission with a power penalty of less than 2 dB over a wide temperature range.     

A 6 Gb/s transmitter with data-dependent jitter reduction technique for displayport physical layer

In this paper, a 6 Gb/s transmitter with data-dependent jitter (DDJ) reduction technique for DisplayPort physical layer is presented. We propose a novel technique to minimize DDJ introduced while the output driver is operating with pre-emphasis mode, which is called DDJ reduction technique. The output driver circuit is designed in 0.13 μm 1P6 M CMOS process and fully compliant to the DisplayPort standard. With the proposed technique, observed DDJ at the output of the driver is reduced from 10 ps to under 1 ps while the output driver producing 400 mV output swing with 6 dB pre-emphasis. The output driver consumes minimum 66 mW and adopts 1.2 V supply voltage for core and 3.3 V supply voltage for I/O including pre-drivers.     

A 3-V fully differential distributed limiting driver for 40-Gb/s optical transmission systems

A fully differential 40-Gb/s electro-absorption modulator driver is presented. Based on a distributed limiting architecture, the circuit can supply up to 3.0-V/sub pp/ (peak-to-peak) per side in a 50-/spl Omega/ load at data rates as high as 44 Gb/s. Both the input and the output are internally matched to 50 /spl Omega/ and exhibit return loss of better than 10 dB up to 50 GHz. Additional features of the driver include the use of a single -5.2-V supply, output swing control (1.7-3.0-V/sub pp/ per side), dc output offset control (-0.15 V to -1.1 V), and pulsewidth control (30% to 66%). The driver architecture was optimized based on a comprehensive analytical derivation of the frequency response of cascaded source-coupled field-effect transistor logic blocks using both single and double source-follower topologies.     

SiGe MMIC power amplifier with on-chip lineariser for X-band applications

An X-band linear power amplifier with an on-chip lineariser is developed using a 0.25 mum SiGe HBT BiCMOS process. The proposed on-chip lineariser improves the 1 dB compression to as much as 3.4 dB with no additional DC power consumption. Under a 3.3 V DC power supply, the single-stage cascode amplifier shows a measured small-signal gain of 12.2 dB and output PI dB of 20.8 dBm, with power added efficiency of 27.4% at the operating frequency range 8.5-10.5 GHz.     

Fully electrical 40-Gb/s TDM system prototype based on InP HEMTdigital IC technologies

This paper presents a fully electrical 40-Gb/s time-division-multiplexing (TDM) system prototype transmitter and receiver. The input and output interface of the prototype are four-channel 10-Gb/s signals. The prototype can be mounted on a 300-mm-height rack and offers stable 40-Gb/s operation with a single power supply voltage. InP high-electron mobility transistor (HEMT) digital IC's perform 40-Gb/s multiplexing/demultiplexing and regeneration. In the receiver prototype, unitraveling-carrier photodiode (UTC-PD) generates 1 V_pp output and directly drives the InP HEMT decision circuit (DEC) without any need for an electronic amplifier. A clock recovery circuit recovers a 40-GHz clock with jitter of 220 fs_pp from a 40-Gb/s nonreturn-to-zero (NRZ) optical input. The tolerable dispersion range of the prototype within a 1-dB penalty from the receiver sensitivity at zero-dispersion is as wide as 95 ps/nm, and the clock phase margin is wider than 70° over almost all the tolerable dispersion range. A 100-km-long transmission experiment was performed using the prototype. A high receiver sensitivity [-25.1 dBm for NRZ (2⁷-1) pseudorandom binary sequence (PRBS)] was obtained after the transmission. The 40-Gb/s regeneration of the InP DEC suppressed the deviation in sensitivity among output channels to only 0.3 dB. In addition, four-channel 40-Gb/s wavelength-division-multiplexing (WDM) transmission was successfully performed     

A 3.1- to 8.2-GHz zero-IF receiver and direct frequency synthesizer in 0.18-/spl mu/m SiGe BiCMOS for mode-2 MB-OFDM UWB communication

A direct conversion receiver for ultra-wideband (UWB) applications operates for 3.1 to 8.2 GHz and gives a noise figure of 3.3 to 4.1 dB and a conversion gain of 52 dB. The chip includes the RF receive chain and a 16-GHz quadrature VCO to generate seven carrier frequencies from 3.4 to 7.9 GHz. The circuit was fabricated in a 0.18-/spl mu/m SiGe BiCMOS process and consumes 88 mA from a 2.7-V supply.     

Highly Linear Ku-Band SiGe PIN Diode Phase Shifter in Standard SiGe BiCMOS Process

This letter presents a fully integrated highly linear 4-bit SiGe PIN diode phase shifter MMIC for Ku-band phase-array application in the standard SiGe BiCMOS process. High-performance customized SiGe PIN diode switches are employed for high linearity and low insertion loss. The use of differential inductors in the hybrid switched filters makes this phase shifter compact in size. Measurements show 20 dB ${pm}5$ dB input/output return loss, less than ${pm} 1.8^{circ}$ phase variation, and maximum 37 dBm input-referred IP3 over the 14.5–15.5 GHz frequency range, while this phase shifter draws an average current of 3.5 mA from a 3.3 V power supply. To the authors' best knowledge, this 4-bit phase shifter MMIC achieves the highest linearity at Ku-band in the standard SiGe BiCMOS process without utilizing any post-fabrication process for low loss transmission lines.      

10-Gb/s modulator drivers with local feedback networks

A novel intrinsic collector-base capacitance (C/sub CB/) feedback network (ICBCFN) was incorporated into the conventional cascode and series-connected voltage balancing (SCVB) circuit configurations to implement 10-Gb/s modulator drivers. The drivers fabricated in 0.35-/spl mu/m SiGe BiCMOS process could generate 9 V/sub PP/ differential output swings with rise/fall time of less than 29 ps. Also, the ICBCFN was modified as an intrinsic drain-gate capacitance feedback network (IDGCFN) to implement drivers with differential output swing of 8 V/sub PP/ in 0.18-/spl mu/m CMOS process. The power consumption is as low as 0.6 W. The present work shows that the driving capability is greater than that of the currently reported silicon-based drivers.     

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

A 45-Gb/s BiCMOS decision circuit operating from a 2.5-V supply is reported. The full-rate retiming flip-flop operates from the lowest supply voltage of any silicon-based flip-flop demonstrated to date at this speed. MOS and SiGe heterojunction-bipolar-transistor (HBT) current-mode logic families are compared. Capitalizing on the best features of both families, a true BiCMOS logic topology is presented that allows for operation from lower supply voltages than pure HBT implementations without compromising speed. The topology, based on a BiCMOS cascode, can also be applied to a number of millimeter-wave (mm-wave) circuits. In addition to the retiming flip-flop, the decision circuit includes a broadband transimpedance preamplifier to improve sensitivity, a tuned 45-GHz clock buffer, and a 50-/spl Omega/ output driver. The first mm-wave transformer is employed along the clock path to perform single-ended-to-differential conversion. The entire circuit, which is implemented in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe HBT, consumes 288 mW from a 2.5-V supply, including only 58 mW from the flip-flop.     

5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 μm SiGe BiCMOS technology and occupy 1.12×1.25 mm2 die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85℃ converges within±3 dB. The total current consumption is 45 mA under a 2.85 V power supply.     

一种2.4 GHz全集成SiGe BiCMOS功率放大器

针对2.4 GHz 802.11 b/g无线局域网(WLAN)的应用,该文设计了一种单片全集成的射频功率放大器(PA)。由于在自适应偏置电路中采用异质结晶体管(HBT)和电容构成的简单结构提高PA的线性度,因此不增加PA的直流功耗、插损和芯片面积。在基极偏置的DC通路中采用电阻负反馈实现温度稳定功能,有效避免热崩溃的同时不引起射频损耗。采用了GRACE 0.18mSiGe BiCMOS 工艺流片,芯片面积为1.56 mm2,实现了包括所有偏置电路和匹配电路的片上全集成。测试结果表明,在2.4-2.5 GHz工作频段,PA的小信号S21增益达23 dB,输入回波损耗S11小于-15 dB。PA的 1 dB 输出压缩点的线性输出功率为19.6 dBm,功率附加效率为20%,功率增益为22 dB。