28 nm多晶硅硬掩模刻蚀中的棒状颗粒缺陷与对策分析

在摩尔定律的影响下,半导体制造的线宽尺寸逐步到达极限。当前28 nm及以下工艺制程中,多晶硅栅极刻蚀普遍采用双层联动的硬掩模刻蚀加多晶硅刻蚀的方法,可以实现关键尺寸的有效控制,但同时也增加了颗粒缺陷的发生率。针对多晶硅硬掩模刻蚀(Polysilicon Hard Mask Etch, P1HM-ET)过程中出现的棒状颗粒缺陷,分析了缺陷的来源和形成机理。通过精准调控刻蚀结束后静电卡盘(Electrostatic-Chuck, ESC)对晶圆的释放时间和自身电荷的释放时间来加强刻蚀腔体内颗粒的清除和减小晶背静电吸附作用。结果显示,当晶圆释放时间增加2 s, ESC电荷释放时间增加6 s后,减少了约80%的棒状颗粒缺陷。通过调控相关联的工艺参数来减少缺陷,可以有效减少消耗性零件的使用,从而降低生产成本。     

纳米尺度多晶硅微结构刻蚀研究

以HBr作为刻蚀气体,采用ICP金属刻蚀系统对气体流量、刻蚀压力、离子源功率、偏压功率等工艺参数与刻蚀速率、刻蚀选择比和侧壁垂直度的对应关系进行了大量工艺实验。借助理论分析和工艺条件的优化,开发出一套可满足制备侧壁垂直度的纳米尺度多晶硅密排线结构的优化刻蚀工艺技术。实验结果表明:当采用900 W的离子源功率、11 W的偏压功率、25 cm3/min流量的HBr气体和3 mTorr(1 mTorr=0.133 3 Pa)刻蚀压力的工艺条件时,多晶硅与二氧化硅的刻蚀选择比大于100∶1;在保持离子源功率、偏压功率、气体流量不变的条件下,单纯提高反应腔工艺压力则会大幅提高上述选择比值,同时损失多晶硅和二氧化硅的刻蚀均匀性;HBr气体流量的变化在上述功率及反应腔工艺压力的工艺范围内,对多晶硅与二氧化硅的刻蚀选择比和多晶硅刻蚀的形貌特征均无显著影响。采用上述优化的刻蚀工艺条件,配合纳米电子束光刻技术成功得到多晶硅纳米尺度微结构,其最小线宽为40 nm。     

CCD多晶硅刻蚀技术研究

CCD晶硅刻蚀相比于传统CMOS工艺的多晶硅刻蚀需要多晶硅对氮化硅更高的刻蚀选择比,更长的过刻蚀时间.采用Cl2+He,Cl2+He+O2,Cl2+He+O2+HBr三种工艺气体组分在Lam4420机台进行了多晶硅刻蚀实验,研究了不同气体配比、不同射频功率对刻蚀速率、选择比、条宽、侧壁形貌等参数的影响.通过优化工艺参数,比较刻蚀结果,最终获得了适合于CCD多层多晶硅刻蚀的工艺条件.     

一种多晶硅掩膜层湿法去除的改进研究

在集成电路制造工艺中,附着在Si片表面的杂质颗粒一直是影响晶圆良率的重大因素,其中在栅极多晶硅刻蚀后的氮氧化硅(SiON)掩膜层湿法去除工艺中,所使用的热磷酸(H3PO4)湿法刻蚀尤其容易产生杂质颗粒.详细分析了热H3PO4湿法刻蚀中杂质颗粒的形成机理,并且提出三种不同的解决途径,然后通过具体实验数据比较得出解决热H3PO4湿法刻蚀后杂质颗粒问题的最佳方案,为集成电路制造企业提供了理论基础和实践依据.     

硅化钨/多晶硅复合栅的反应离子刻蚀工艺研究

本文介绍用SF_6+O_2,SF_6+Cl_2作腐蚀剂,反应离子刻蚀(RIE)的硅化钨/多晶硅复合栅工艺。着重研究了各工艺参数的改变对硅化钨和多晶硅刻蚀结果的影响,和刻蚀复合栅结构的最佳工艺条件。     

亚硝酸钠刻蚀液对多晶硅表面陷阱坑形貌的影响

酸刻蚀多晶硅表面技术是当前太阳能研究的热点之一。利用亚硝酸钠比硝酸钠氧化能力弱的特点,在普通酸刻蚀液中用亚硝酸钠取代硝酸配制多晶硅表面刻蚀液,然后在相同的工艺条件下刻蚀多晶硅表面。实验样品的SEM显示:含有NaNO2酸刻蚀液使多晶硅表面能布满蚯蚓状的腐蚀坑,腐蚀坑的深度比传统的酸刻蚀的陷阱坑深,而且密度分布比较均匀,样品平均反射率下降到23.5%,与传统配方酸刻蚀液刻蚀的多晶硅表面相比,平均反射率下降了8%左右。     

VLSI中双层多晶硅结构的剖面研究

本文对VLSI中双层多晶硅结构的剖面及用于结构成形的干法腐蚀技术进行了研究,获得了优化的剖面结构.研究分析表明,多晶硅Ⅰ的侧墙越倾斜,则双层多晶硅结构越佳.改变刻蚀条件可以有效地调节横向对纵向的刻蚀速率比δ,满意地获得多晶硅Ⅰ侧墙倾角α为49°左右;多晶硅Ⅱ采用二步刻蚀工艺.结果既消除了3μm工艺中用各向异性的RIE刻蚀易出现的多晶硅Ⅱ沿多晶硅Ⅰ侧墙的残留造成的相邻字线短路现象,又保证了线宽的精确控制,对下层SiO_2只有轻微的侵蚀.为VLSI制造提供了适用的工艺结构设计和加工技术,成功地研制出了64K DRAM合格样品.     

RMOS器件中硅槽及多晶硅栅的刻蚀

ＲＭＯＳ（Ｒｅｃｔａｎｇｕｌａｒ Ｇｒｏｏｖｅｄ ＭＯＳ）器件因具有独特的性能而得到较好的应用。本文介绍用ＲＩＥ设备进行ＲＭＯＳ器件硅槽刻蚀的工艺，并对填满硅槽内的多晶硅栅的刻蚀亦作了研究。选择适当的工艺条件，可刻蚀出形貌较好的硅槽，并可在刻蚀完多晶硅后保持硅槽内多晶硅栅形貌完好 。     

0.35μm CMOS多晶硅栅刻蚀工艺研究

本文主要研究0.35μm CMOS多晶硅栅刻蚀工艺中“硅LOSS”及“T腰”问题的形成机理.在不改变产品工艺流程的前提下,对多晶硅栅刻蚀工艺进行优化,提出“两步ME法”优化了刻蚀形貌,改善了硅LOSS、T腰的问题.满足0.35μm CMOS多晶形貌及工艺要求,具有一定的理论指导和实际意义.     

两步刻蚀多晶硅提高图形陡直度

微电子机械系统中关键工艺之一就是刻蚀出高深宽比的图形。本文对掺磷多晶硅反应离子刻蚀（ＲＩＥ）进行了研究,采用两步刻蚀工艺,ＳＦ６,ＣＦ４,Ｃｌ２ＣＦ三种气体组合,从原来４５度的各向同性刻蚀提高到７３度以上的各向异性蚀。射频功率３９０瓦时,刻蚀速率每分钟２００ｎｍ。对３．５微米厚的多晶硅,刻蚀时间在２０分钟左右,基本上达到要求。     

Optimization of ohmic contact and adhesion on polysilicon in MEMS-NEMS wet etching process

This paper presents the optimization of polysilicon doping and metallization to form ohmic contact with etching resistance. Indeed, polysilicon doped by ion implantation and ohmic contacts are an important and interesting part of integrated circuit technology or MEMS and NEMS. LPCVD-polysilicon doping parameters, such as ion energy, dose, and annealing were investigated. In particular a superficial implantation realized after a deep implantation enables one to slightly decrease the polysilicon resistivity while the contact resistance is reduced. And ohmic contacts with wet etching resistance were realized by depositing the different metallization stacks. We demonstrate that ohmic contact pad Cr/Pt/Au has provided a good adhesion on LPCVD-polysilicon after wet etching.     

The honeycomb-shape capacitor structure for ULSI DRAM

A way to increase the charge stored in polysilicon capacitors using surface modulation technology is proposed. Asperities on the polysilicon surface are achieved by reactive ion etching (RIE) of the polysilicon, using the oxide at the grain boundary as a mask. The fabricated polysilicon electrode has a honeycomb shape. With this structure, the capacitance is increased by four times for a polysilicon storage electrode of 250-nm thickness. The leakage current is comparable to that of convection stacked capacitors (STCs)     

Dry etching technology for 1-µm VLSI fabrication

A dry etching technology for 1-µm VLSI has been developed. This technology led to successful fabrication of a 1-µm 256-kbit MOS RAM using electon-beam direct writing and molybdenum-polysilicon double-gate structure. Silicon nitride, silicon dioxide, phosphosilicate glass, polysilicon, single-crystal silicon, molybdenum, and aluminum are etched by parallel-plate RF diode reactors. Resist patterns are used as etching masks. The negative resist is CMS and the positive resist is FPM. Plasma polymerization is found to have significant effect on etching selectivity, undercutting, and residue. Directional etching profiles are realized and 1-µm patterns with less than 0.05-µm undercutting are obtained. High etching selectivities are achieved. Methods for preventing and removing contamination as well as damage are established. With these, dry etching proves to bring no adverse effects on device characteristics. Pattern-width fluctuations caused by negative-resist pattern foot are decreased to below 0.1 µm by a new foot trimming technique. Resist step coverage is also clarified.     

Nanoscale structure formation by plasma etching

Process of isotropic plasma etching of polysilicon to form nanostructures has been developed and optimized. Dependences of the technological characteristics of the isotropic plasma etching process of polysilicon on its operational parameters have been obtained. The results were to form nanowire silicon field effect transistors and a sensitive vibro-resonant nanoelement for an atom mass sensor.     

Ultra uniform arrays of micro patterns on large area substrate by employing wet chemical etching

A wet chemical selective etching process is presented to delineate ultra-uniform micro patterns in the form of arrays of sensor chips of 4 mm×4 mm size in the matrix of 9×9 on a 3″ diameter silicon substrate with uniform physical and electrical characteristics. The selective etching of thin film is confined to the top area by masking its outer edges. This leads to uniform etching of the entire film leading to ultra-uniform delineation of arrays of micro patterns. The process has been verified over the selective etching of doped polysilicon in defining the polysilicon resistors and subsequently has been applied on realizing Ti/Au interconnecting lines using wet chemical etchant. Experimental results are presented with physical and electrical characteristics of the patterned structures in the statistical form over the substrate surface. SEM analysis is carried out for physical dimension measurement and standard deviation of 0.0040 is observed in polysilicon micro patterning. The process is competitive with reactive ion etching (RIE) in terms of yield, reliability and repeatability with cost effectiveness in a production environment. Methodology of ultra-uniform etching on entire substrate area is developed in support of the experimental results. The ratio of Top Surface Area (TSA) and Total Exposed Surface Area (TESA) is shown as crucial parameter for the uniform etching of thin films.     

多晶硅清洗设备研究

介绍了多晶硅清洗设备,即：硅块、硅棒／硅芯清洗设备。并对其结构设计进行阐述。对设备关键部件-工艺槽、机械臂的设计进行了详细的说明。该设备满足了大规模生产的需要,能够保证产品的品质及生产效率。     

大面积非光刻纳米电极间隙的制备

A lithography-independent and wafer scale method to fabricate a metal nanogap structure is demonstrated. Polysilicon was first dry etched using photoresist （PR） as the etch mask patterned by photolithography. Then, by depositing conformal SiO2 on the polysilicon pattern, etching back SiO2 anisotropically in the perpendicular direction and removing the polysilicon with KOH, a sacrificial SiO2 spacer was obtained. Finally, after metal evaporation and lifting-off of the SiO2 spacer, an 82 nm metal-gap structure was achieved. The size of the nanogap is not determined by the photolithography, but by the thickness of the SiO2. The method reported in this paper is compatible with modern semiconductor technology and can be used in mass production.     

Effects of plasma etching chemistry and post-processing on themechanical adhesion and electrical contact of double polysilicon layerstructures

Double polysilicon layer structures separated by a silicon nitride layer are frequently used as structural multilayers in surface micromachining. In this paper the effect of three types of plasma etching chemistries for nitride patterning and post-processing on the characteristics of both mechanical adhesion and electrical contact resistance between the two polysilicon layers is investigated. It was found that all three chemistries yielded good mechanical adhesion between the two polysilicon layers. Both the chemistry based on CF₄ /SF₆, with a poor selectivity (0.7) of etching nitride over the underlying polysilicon layer, and the chemistry based on CHF ₃/CF₄, with a selectivity of 3, provided good electrical contact. The chemistry based on CHF₃/N₂, which yielded a selectivity of 15, on the other hand, resulted in a polymer film between the two polysilicon layers, resulting in electrical insulation. This polymer film can be effectively removed by using post-processing, which involves in-situ oxygen plasma treatment. Therefore, a chemistry such as that based on CHF₃/CF₄ can be applied when the lower polysilicon thickness allows a moderate selectivity, whereas the CHF₃/N ₂ chemistry is favored when high-selectivity is required. The latter, however, requires in-situ post-processing