Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO₂ nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime t_L = 1.64 × 10¹⁰ s, which agreed well with the t_L = 1.92 × 10¹⁰ s measured at low gate stress voltage, whereas the conventional model overestimates t_L by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating t_L of high-k nMOSFETs.     

Degradation of pMOSFETs due to hot electron induced punchthrough

This paper proposes a method which can separate the parasitic effect from the drain current I_d vs. gate voltage V_g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I_d vs. V_g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I_d vs. channel width W at each V_g to W = 0 μm. The I_d vs. V_g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V_th of the parasitic MOSFET but increased V_th of the main MOSFET. These two opposite behaviors of V_th resulted in little HEIP-induced shift of V_th at W = 2.5 μm. | V_d | to secure ten-year HEIP lifetime of 10% shift of V_th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.     

In-plane electrical bistability of photochromic diarylethene/Cu composite film

Electrical bistability is an essential property for memory devices. We report here the in-plane electrical bistability of photochromic diarylethene (DAE)/Cu composite film, which is prepared by Cu vapor deposition on the DAE surface with a low glass-transition temperature. The low-current level around 10⁻⁸ A was switched to a high-current level of ca. 10⁻⁴ A at a low threshold voltage (V_th) in the first voltage sweep. Once this switching occurred, the high-current level was kept in the second voltage sweep, and electrical bistability was achieved for the in-plane current. V_th was distributed in a wide range of voltages (0.5–10 V), and the colored sample obtained by the UV irradiation showed a relatively higher V_th than the colorless sample. The highest ON–OFF ratio in current was ca. 10⁶. The origin of the bistability attributed to the electrical breakdown in the insulated lines that was consisted of DAE in Cu film. The in-plane bistability of the DAE/Cu composite film has good retention time (>60 min) and readout-cycle endurance (>10⁶ cycles), indicating that it is suitable for write-once organic semiconductor memory characteristics.     

Novel organic inverters with dual-gate pentacene thin-film transistor

We report on the fabrication and characterization of dual-gate pentacene organic thin-film transistors (OTFTs) with plasma-enhanced atomic-layer-deposited (PEALD) 150 nm thick Al₂O₃ as a bottom-gate dielectric and PEALD 200 nm thick Al₂O₃ as a top-gate dielectric. The V_th of dual-gate OTFT has changed systematically with the application of voltage bias to top-gate electrode. When voltage bias from −10 V to 10 V is applied to top gate, V_th changes from 1.95 V to −9.8 V. Two novel types of the zero drive load logic inverter with dual-gate structure have been proposed and fabricated using PEALD Al₂O₃ gate dielectrics. Because the variation of V_th due to chemical degradation and the spatial variation of V_th are inherent in OTFTs, the compensation technology by dual-gate structure can be essential to OTFT applications.     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

High power 4H–SiC pin diodes (10 kV class) with record high carrier lifetime

The hole lifetime τ_p in the n-base and isothermal (pulse) current–voltage characteristics have been measured in 4H–SiC diodes with a 10 kV blocking voltage (100 μm base width). The τ_p value found from open circuit voltage decay (OCVD) measurements is 3.7 μs at room temperature. To the best of the authors’ knowledge, the above value of τ_p is the highest reported for 4H–SiC. The forward voltage drops V_F are 3.44 V at current density j = 100 A/cm² and 5.45 V at j = 1000 A/cm². A very deep modulation of the blocking base by injected non-equilibrium carriers has been demonstrated. Calculations in term of a simple semi-analytical model describe well the experimental results obtained.     

Temperature dependences of threshold voltage and drain-induced barrier lowering in 60 nm gate length MOS transistors

The temperature dependence of threshold voltage (V_T) and drain-induced barrier lowering (DIBL) characteristics for MOS transistors fabricated with three different threshold voltage technologies are studied. We found that the technique employed to adjust the V_T value make the devices to be not well-scaled for short-channel effects for ultra-short devices at low temperatures. For devices with a short gate length (L<90 nm) and being fabricated using the low threshold voltage (low-V_T) technology, both the temperature dependencies of threshold voltage and DIBL are different to the standard-V_T and high-V_T ones. Abnormally large values of DIBL were found for low V_T-devices because of the significant encroachment of drain depletion region on the channel region. On the other hand, the high substrate doping in high-V_T process makes the devices to have a larger junction depth than that used in the standard process. It causes a poorer DIBL for short-channel devices. Hence the best scaling or design of the devices at room temperature does not imply that they should also be good at low temperatures, especially for L = 60 nm fabricated using the low-V_T process. Different device design and process optimization are required for devices to be operated at temperatures beyond the nominal range.     

All-inkjet printed organic transistors: Dielectric surface passivation techniques for improved operational stability and lifetime

We report about the use of a printed pentafluorothiophenol layer on top of the dielectric surface as a passivation coating to improve the operational stability of all-ink-jet printed transistors. Transistors with bottom-gate structure were fabricated using cross-linked poly-4-vinylphenol (c-PVP) as dielectric layer and an ink formulation of an amorphous triarylamine polymer as semiconductor. The resulting TFTs had low turn-on voltage (V_th < |5 V|) and a mobility ≈0.1 cm²/(V s). A comparison of identically fabricated transistors shows that devices with coated dielectric have a higher operational stability than those using bare c-PVP. This conclusion is supported by a quantitative study of the threshold voltage shift with time under continuous operation. Long exposure to the ambient atmosphere causes an increase in the threshold voltage strongly dependent on the used semiconducting ink formulation.     

Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

This paper reports on the effects of the Halo structure variations on threshold voltage (V_th) in a 22 nm gate length high-k/metal gate planar NMOS transistor. Since the V_th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V_th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO₂ dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L₉ array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V_th. The results show that the V_th values have least variance and the mean value can be adjusted to 0.289 V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors.     

Stressing organic light-emitting diode under constant-brightness driving mode

The degradation of the organic light-emitting diodes (OLEDs) was studied under the constant-brightness driving mode. The time-dependent current exhibits a long period of linear increase followed by an exponential increase before the eventually catastrophic failure featured by a vertical increase. A new lifetime T_th is defined as the time for the device to reach the end of the linear increase stage. Similar to the well-known relation between the lifetime and the brightness in the constant-current driving mode, the lifetime and the brightness in the constant-brightness driving mode also fit the formula Lⁿ × T_th = Const., where L is the brightness and n is the acceleration exponent. By examining the current density–voltage–luminance characteristics and the photoluminescence intensity of the devices before and after the stress, it is found that both the reduction of the charge injection efficiency, and the loss of the emissive centers, contribute to the OLEDs’ degradation. The extra power supplied to the device to keep the brightness constant, raises the junction temperature, and eventually leads to the catastrophic failure of the devices.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

High-performance diketopyrrolopyrrole-based organic field-effect transistors for flexible gas sensors

We demonstrate high-performance flexible polymer OFETs with P-29-DPP-SVS in various geometries. The mobilities of TG/BC OFETs are approximately 3.48 ± 0.93 cm²/V s on a glass substrate and 2.98 ± 0.19 cm²/V s on a PEN substrate. The flexible P-29-DPP-SVS OFETs exhibit excellent ambient and mechanical stabilities under a continuous bending stress of 1200 times at an R = 8.3 mm. In particular, the variation of μ_FET, V_Th and leakage current was very negligible (below 10%) after continuous bending stress. The BG/TC P-29-DPP-SVS OFETs on a PEN substrate applies to flexible NH₃ gas sensors. As the concentration of NH₃ increased, the channel resistance of P-29-DPP-SVS OFETs increased approximately 100 times from ∼10⁷ to ∼10⁹ Ω at V_SD = −5 V and V_GS = −5 V.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

Carbazole based A-π-D-π-A dyes with double electron acceptor for dye-sensitized solar cell

Three novel carbazole-based A-π-D-π-A-featured dyes (CSG1–CSG3) have been designed, synthesized for applications in dye-sensitized solar cells and fully characterized with NMR, MS, IR, UV–vis and electrochemical measurements. These dyes share the same donor (N-hexylcarbazole) and acceptor/anchoring group (cyanoacrylic acid), but differs in conjugated linkers incorporated, such as benzene, furan or thiophene, to configure the novel A-π-D-π-A framework for effective electron flow. The power conversion efficiencies were observed to be sensitive to the π-bridging linker moiety. The photovoltaic experiments showed that dye with a benzene linker exhibited a higher open-circuit voltage (0.699 V) compared to thiophene and furan linker. Among all dyes, CSG2 containing a thiophene linker exhibited the maximum overall conversion efficiency of 3.8% (J_SC = 8.90 mA cm⁻², V_OC = 584 mV, FF = 0.74) under standard global AM 1.5 G solar condition. Under similar fabrication conditions, champion dye N719 exhibited the maximum overall conversion efficiency of 6.4% (J_SC = 14.74 mA cm⁻², V_OC = 606 mV, FF = 0.716).     

Benzopyrazine-fused tetracene derivatives: Thin-film formation at the crystalline mesophase for solution-processed hole transporting devices

Benzopyrazine-fused tetracene (TBPy) and its disulfide (TBPyS) bearing alkoxy groups (OCH₃, OC₈H₁₇) were designed and synthesized to obtain π-expanded tetracene derivatives. These derivatives are featured with long-wavelength light absorption property (λ_onset: up to 820 nm), photooxidative stability (half-lives (τ_1/2): 11 times longer than tetracene), and solubility for solution process. The methoxy compounds (TBPy-C1 and TBPyS-C1) were used for single-crystal X-ray crystallographic analysis and single-crystal organic field-effect transistor (OFET) devices showing relationship between packing structures and hole mobilities. The octyloxy compounds (TBPy-C8 and TBPyS-C8) were investigated on solution-processed thin-film formation and hole transport property in thin-film OFET devices. Crystalline mesophase of TBPy-C8 and TBPyS-C8 was characterized by differential scanning calorimetry analysis showing endothermic peaks at 98 and 198 °C on its second heating process and exothermic peaks at 177 and 76 °C on its second cooling process for TBPyS-C8, and played crucial roles in thin-films formation. Hole mobility of 1.7 × 10^?2 cm²/V s (with V_th = ?30 V and I_ON/I_OFF = 10⁴) was obtained for the thin-film OFET device of TBPyS-C8.     

HCS degradation of 5 nm oxide high-voltage PLDMOS

Hot carrier (HC) injection, inducing drain and gate leakage current increase in 5 nm oxide p-channel LDMOS transistors, is investigated. Devices with two different drain implants are studied. At low gate voltage (V_GS) and high drain voltage (V_DS), reduction of the ON-resistance (R_ON) is observed. At stress times at which R_ON almost reaches its constant level, an increase of the drain leakage in OFF state (V_DS = −60 V, V_GS = 0 V) is observed. Longer stress time leads to increased gate leakage and in some cases oxide breakdown. In contrast to what was reported for devices with 25 nm gate oxide thickness, the threshold voltage of 5 nm gate oxide PLDMOS transistors does not drift. The experimental data can be fully explained by hot carrier injection and the oxide damage can be explained by two different and competing degradation mechanisms. By combining experimental data and TCAD simulations we are further capable to locate the hot spot of maximum oxide damage in the accumulation (Acc) region of the PLDMOS.     

Dual-resonance concurrent oscillator

This paper studies a new dual-band CMOS class-C voltage-controlled oscillator (VCO). The oscillator consists of a dual-resonance LC resonator in shunt with two pairs of capacitive cross-coupled nMOSFETs. The proposed oscillator has been implemented with the TSMC 0.18 μm CMOS technology, and it shows a frequency tuning range with two frequency bands and a small tuning hysteresis is measured. The oscillator can generate differential signals at 2.4 GHz and 6.9 GHz and it also can generate concurrent frequency oscillation while the circuit is biased around the bias with frequency tuning hysteresis. With the supply voltage of V_DD = 1.1 V, the VCO-core current and power consumption of the oscillator are 2.90 mA and 3.19 mW, respectively. The die area of the class-C oscillator is 0.9 × 0.97 mm². Overvoltage stress is applied to the oscillator, measurement indicates the concurrent oscillation is sensitive to overvoltage stress.     

Improved performance of nanoporous TiO2 film in dye-sensitized solar cells via ZrCl4 and TiCl4 surface co-modifications

In this study, nanoporous TiO₂ films were modified by a dip-coating process using a mixture aqueous solution of ZrCl₄ and TiCl₄ followed by calcination to prepare a photoanode for dye-sensitized solar cells. Compared with the control film modified with 0.04 mol L⁻¹ TiCl₄, the power conversion efficiency of the TiO₂ film modified with a mixed solution of 0.05 mol L⁻¹ ZrCl₄ and 0.04 mol L⁻¹ TiCl₄, was 18.67% higher because of the improved short circuit current (J_sc) and open circuit voltage (V_oc). The improvement in J_sc was due to the suppression of charge recombination, which was demonstrated by a series of measurements, including electrochemical impedance spectroscopy, monochromatic incident photon-to-electron conversion efficiency spectroscopy, and the open-circuit voltage decay technique. The Mott-Schottky measurement results indicated that the negative shift of a flat band led to the increased V_oc.