NBTI and hot carrier effect of Schottky-barrier p-MOSFETs

The experimental investigation of NBTI and hot carrier induced device degradation in Pt-silicided Schottky-barrier p-MOSFETs has been performed. The investigations on the threshold voltage shifts, the degradation of inverse subthreshold slope, and the decrease of I_ON/I_OFF ratio have been carried out using the modulation of Schottky-barrier height and width. After NBTI and hot carrier stress, the decrease of I_ON could be explained by the lower hole tunneling current through the more increased Schottky-barrier height and the increased I_OFF could be explained by the increase of the amount of electron thermal emission and tunneling through thinner Schottky-barrier into the near drain. After hot carrier stress, it is observed that the threshold voltage shifts to more negative values for all stress gate voltages and the drain current is decreased. The device degradation is more significant as the stress gate voltage decreases.     

A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits

We present an aging analysis which considers variations in chip environment and workload as they are caused by dynamic voltage or frequency scaling, power-down modes, etc. Therefore, we developed a model for NBTI degradation and recovery based on trapping/detrapping. Our model accurately describes the relaxation during detrapping, the quasi-permanent degradation and shows good agreement with measurements from a 65 nm technology. The aging analysis utilizes this model to consider variations in environment and workload. Results show that our analysis can be used for system-level design decisions and reduces substantially estimated degradation.     

Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design.     

Positive charge generation due to species of hydrogen during NBTI phenomenon in pMOSFETs with ultra-thin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with ultra-thin SiON gate dielectrics was investigated. We focused our attention on the behavior of hydrogen atoms released from the interface under NBT stress. From the transient characteristics of pMOSFETs after NBT stresses were stopped, it was found that a portion (60%, in our case) of hydrogen atoms released by the NBT stress remain in a 1.85-nm-thick NO-oxynitride gate dielectric. The existence of the hydrogen in the gate dielectric was shown to lead to the generation of positive charges.     

NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations

Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased.     

Analytical Low Frequency NBTI Compact Modeling with H<Subscript>2</Subscript> Locking and Electron Fast Capture and Emission

Besides reaction-diffusion theory explaining the generation and passivation of interface trap (ΔN_IT), hole trapping/de-trapping in preexisting gate insulator traps and transient charge occupancy in ΔN_IT are also combined to describe the characteristic of NBTI degradation. However, it is found that H₂ locking effect and Electron Fast Capture/Emission play key roles in the NBTI degradation. In this paper, an analytical low frequency AC NBTI compact model has been proposed to accurately predict the shift in threshold voltage. Two fitting parameters (α and F_FAST) have been introduced to account for the H₂ locking and fast electron capture and emission. The comparison between the proposed model and the experimental data has been carried out, and the results show that our proposed can catch the kinetics of NBTI degradation under low frequency AC stress conditions.     

NBTI and hot carrier effect of SOI p-MOSFETs fabricated in strained Si SOI wafer

Comparative study on NBTI and hot carrier effects of p-channel MOSFETs fabricated by using strained SOI wafer and unstrained SOI wafer has been performed, respectively. It is observed that NBTI and hot carrier degradation are more significant in strained SOI devices compared with unstrained SOI devices. Since the devices fabricated in strained SOI wafer are SiGe free strained devices, the more generation of interface states during gate oxidation is the main cause for enhanced NBTI and hot carrier degradation in strained SOI devices.     

On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress

A common framework for interface-trap (N/sub IT/) generation involving broken /spl equiv/Si-H and /spl equiv/Si-O bonds is developed for negative bias temperature instability (NBTI), Fowler-Nordheim (FN), and hot-carrier injection (HCI) stress. Holes (from inversion layer for pMOSFET NBTI, from channel due to impact ionization, and from gate poly due to anode-hole injection or valence-band hole tunneling for nMOSFET HCI) break /spl equiv/Si-H bonds, whose time evolution is governed by either one-dimensional (NBTI or FN) or two-dimensional (HCI) reaction-diffusion models. Hot holes break /spl equiv/Si-O bonds during both FN and HCI stress. Power-law time exponent of N/sub IT/ during stress and recovery of N/sub IT/ after stress are governed by relative contribution of broken /spl equiv/Si-H and /spl equiv/Si-O bonds (determined by cold- and hot-hole densities) and have important implications for lifetime prediction under NBTI, FN, and HCI stress conditions.     

Passive mode locking of lasers with the optical Kerr effect modulator

A detailed analytical investigation is presented of a nonlinear device termed the optical Kerr effect modulator (OKEM) which is used to passivelyQswitch and mode lock high-power lasers. Experimentally, an OKEM employing two standard quarter-wave plates is used to passively mode lock the Nd:glass laser. The mode-locking threshold dependence upon the parameters of the OKEM transmission function is definitively established. Pulsewidths and spectral measurements are given for the train of ultrashort pulses from the glass laser mode locked with the OKEM using two different Kerr liquids. The analytical and experimental results together indicate that the OKEM technique is a versatile and viable alternative and in addition overcomes most of the shortcomings intrinsic to the saturable absorber technique. The non-resonant nature of the OKEM suggests that it should find immediate application as a passiveQ-switching and mode-locking element for a Variety of lasers, including dye lasers, UV lasers, the CO2laser, and, notably, the high-power iodine laser.     

Modeling of NBTI saturation effect and its impact on electric field dependence of the lifetime

Negative Bias Temperature Instability of pMOSFETs is investigated under various stress gate voltages and temperatures. It is shown that degradation tends to saturate and the dependence of lifetime on electric field (E_ox) is expressed as a power-law of E_ox. We propose new empirical and kinetic models. The E_ox dependence of the lifetime described by the power-law is derived from our empirical model describing the saturation of degradation. Moreover, our kinetic model explains the saturation behavior.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.     

Mode locking the Nd:Glass laser with BDN: Measurements of dye recovery times and laser pulse lengths

The recovery times for transient bleaching of theQ-switch dye bis(4-dimethylaminodithiobenzil)nickel (BDN) in the solvents dichlorethane and iodoethane have been determined. The lengths of pulses from an Nd:glass laser mode locked with BDN have also been measured by means of the two-photon fluorescence technique.     

High voltage applications and NBTI effects of DT-pMOSFETS with reverse Schottky substrate contacts

In this study, the characteristics of DT-pMOSFETs are discussed using the reverse Schottky substrate contacts. With this diode, the DTMOS can be operated at high voltage and temperature. In addition, it exhibited an improved driving current, DIBL, transconductance, and subthreshold slope. The driving current for DTMOS was 20% larger, and was 12 mV improved for DIBL under DTMOS operation. Furthermore, the NBTI effects of DTMOS were also reported for the first time. This is because DTMOS could operate just below 0.7 V of V_G due to the junction turn-on behavior. It is interesting to note that the shift of the ΔV_TH of pMOSFETs under NBTI measurement was significantly alleviated in the DT operating mode, about 30 mV improved after 10,000 s stressing, due to the alleviated electrical field across the gate oxide which was due to the substrate bias and the threshold voltage adjustment under DTMOS operation.     

Analytical one-dimensional current-voltage model for FD SOI MOSFETs including the effect of substrate depletion

In this paper, we present an analytical one-dimensional current-voltage model for silicon-on-insulator (SOI) MOSFETs under full depletion (FD). Our model has been developed from the first principles, and it not only includes the effects of source-drain series resistances, self-heating, and parasitic BJT, which are essential to FD SOI device modeling, but also includes another important effect of substrate depletion, for the first time in the literature, which is of vital significance for FD SOI devices having small film thickness and low substrate doping. The results of the drain current obtained from our model show a much better match with the experimental data, with the maximum error being only 9.41%, which is reasonably lower than the maximum error of 15.04% produced by the model of Yu et al., and marginally better than the error of 11.5% of the model of Hu and Jang. It must be noted that, though the improvements achieved in terms of accuracy are not that significant, yet unlike other models, ours is based on a simplified one-dimensional analytical approach, which is absolutely free from iterations, and hence, there is a huge improvement in terms of computational efficiency, which establishes its practical significance.     

A simple power diode model with forward and reverse recovery

The basic diode charge-control model used in SPICE is extended by employing the lumped charge concept of J.G. Linvill and J.F. Gibbons (1961) to derive a set of model equations from simplified device physics. Both forward and reverse recovery phenomena are included as well as emitter recombination. The complete model requires only seven relatively simple equations and three additional device parameters beyond the genetic SPICE diode model. A major feature of the model is that the same equations are valid through all regions of operation     

Analytical model and characterization of abnormally structured MOSFETs

Electrical characteristics of abnormally structured n-MOSFETs having uncontacted active regions are experimentally investigated using test devices with various gate widths. Linear resistance and saturation drain current of the devices are estimated by a simple schematic model, which consists of parallel-connected conventional devices having parasitic resistors. A comparison of experimental results of conventional and abnormal devices gives the parasitic resistance caused by abnormal active structure. The increment rate of the parasitic resistance depending on gate width shows two categories, which are logarithmic increment at narrow device and exponential increment at wider device. The performance degradation in the wider device is also explained by the reduction of effective channel area. The suggested model provides a physical analysis of the abnormal transistor and shows good agreement with the measured drain current in linear and saturation regions for both forward- and reverse-modes.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

Multimode effects on the evolution and long-term stability of apassively mode-locked laser under pulsed injection locking

A multidimensional extension of the injection locking of CW lasers has been recently presented and experimentally verified when both a passively and an actively mode-locked laser were locked to injected coherent pulse trains. Harmonic injection locking of a passively mode-locked laser, where a subset of the laser cavity modes were locked to the injected signal, was also recently realized in a fiber laser to yield trains of 6-ps pulses at rates of up to 40 GHz. In this paper, the multimode injection-locking process is addressed with an emphasis on the long-term dynamics of the laser, pulse buildup under injection locking, memory effects, noise mechanism as well as potential applications, e.g., optical signal regeneration. Using a recently introduced formalism for describing passively mode-locked lasers, the experimental results are compared to numerical simulations     

The optimum fin width in p-MuGFETs with the consideration of NBTI and hot carrier degradation

Generally it is known that NBTI degradation increases with decrease of a channel width in p-MOSFETs but hot carrier degradation decreases. In this work, a guideline for the optimum fin width in p-MuGFETs is suggested with consideration of NBTI and hot carrier degradation. Using the device lifetime defined as the stress time necessary to reach ΔV_TH = 10 mV, the optimum fin widths have been extracted for different stress voltages and temperatures. When a fin width is narrower than the optimum fin width, the device lifetime is governed by the NBTI degradation. However, when fin width is wider than the optimum fin width, the device lifetime is dominantly governed by hot carrier degradation. The optimum fin width decreases with the increase of the stress voltage but it increases with the increase of the stress temperature.