Measurement and numerical modeling of short-channel MOSFET gate capacitances

The gate-to-source and gate-to-drain capacitance of long-and short-channel n-MOSFET's have been measured and simulated using a two-dimensional numerical simulator that allows different inversion layer carrier mobility models to be used. Comparison of the experimental and simulated data indicates velocity saturation effect is seen in the capacitance data of the short-channel devices. Transverse-field dependence of the mobility is also found to be necessary to account for the experimental data.     

Two-dimensional numerical modeling of lightly doped nano-scale double-gate MOSFET

A two-dimensional numerical solution of electrostatic potential and electric field profiles are presented for lightly doped nano-scale Double-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistor (DG-MOSFET). We have developed quasi-static (QS) model for evaluating bulk and inversion charges based on symmetric linearization model. We have also shown the non-quasi-static (NQS) effect on the charge due to a time varying gate voltage. It is seen that various symmetries of DG-MOSFET characteristics with respect to source/drain interchange is maintained in quasi-static as well as non-quasi-static version of the symmetrically linearized model. The variation of the threshold voltage with the varying width of the device is evaluated and presented. The results have been compared and contrasted with reported analytical model for QS condition for the purpose of verification of the model. The variation of threshold voltage along the width of the device is also predicted. This numerical model can be extended to analyze the transport phenomenon in sub 30 nm channel length DG-MOSFETs.     

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical valueW_{min}which is about 1 µm for 200-A gate oxide 7000-A field oxide and2 times 10^{16}cm^-3substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.     

Inviance of the Hall effect MOSFET to gate geometry

A theoretical and experimental evaluation was made of the Hall Effect MOSFET with various gate geometries. The numerical model of Fry and Hoey agreed very well with the experimental results for the circular, rectangular and diamond geometries studied. No variation of Hall voltage with gate geometry was observed. This result is consistent with elementary complex variable theory and is in direct disagreement with some published results. The discrepancy can be accounted for by this author's approach to device characterization. Piezoelectric phenomena were observed and their effect on device design described.     

MOS器件的栅氧化层抗HPM击穿效应的研究

随着集成度的不断提高,集成电路的绝缘层越来越薄.如CMOS器件绝缘层的典型厚度约为0.1μm,其相应的耐击穿电压在80～100V间.当器件特征尺寸进人深亚微来时,栅氧化层厚度仅为数纳米,而器件工作的电源电压却不宜降低,这使栅氧化层工作在较高的电场强度下,栅氧化层的抗电性能成为一个突出的问题.往往一个能量不算大的电磁脉冲,就可以让集成电路的栅氧击穿,将直接导致MOS器件的失效.     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance

The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.     

Two-dimensional numerical simulation of side-gating effect in GaAsMESFETs

Two-dimensional device simulations that confirm that the side-gating effect in GaAs MESFETs occurs on semi-insulating substrates containing hole traps are discussed. A negative voltage applied on a side gate, a separate n-type doped region, causes an increase in the thickness of the negatively charged layer at the FET channel interface in the substrate, through hole emission from hole traps. The FET channel current is modulated by the electron depletion of the n-type channel, which results from the compensation for the extension of the negatively charged layer at the n-i interface into the i-substrate containing hole traps. The magnitude of the drain current reduction is determined by the total acceptor concentration in the substrate and the donor concentration of the channel. However, the magnitude is independent of the side-gate distances     

A novel trench gate floating islands power MOSFET (TG-FLIMOSFET): Two-dimensional simulation study

Novel trench gate floating islands MOSFET (TG-FLIMOSFET) designed using the concept of “Opposite Doped Buried Regions” (ODBR) and floating islands (FLI) along with trench gate technology is proposed and verified using two-dimensional simulations. The conventional FLIMOSFET experimentally demonstrated recently, although offers lowest on-resistance in the low voltage range, however, suffers from quasi-saturation effect like any other power MOSFETs. The proposed TG-FLIMOSFET demonstrated to obtain about 30% reduction in peak electric field in drift region of the proposed device. TG-FLIMOSFET also demonstrates quasi-saturation free forward and transconductance characteristics, improved synchronous rectifying characteristics, identical breakdown voltage, reduced on-resistance and increased transconductance ‘gm’ when compared with the conventional FLIMOSFET for various trench geometries. The proposed device breaks the limit set by the conventional FLIMOSFET approximately by a factor of 10. A possible process flow sequence to fabricate the proposed device commercially by integrating multi-epitaxial process with trench gate technology is also presented.     

Trench isolation step-induced (TRISI) narrow width effect on MOSFET

We report a new narrow-width effect that manifests as an increase in threshold voltage V/sub th/ and in its standard deviation /spl sigma//sub Vth/ as the width W of a MOSFET is reduced to be comparable to the trench isolation step height and the gate polysilicon thickness. At such small W the conformal deposition of polysilicon across the step between the active and isolation regions induces the polysilicon gate to be thicker over the active region. This increased thickness is shown to increase the poly depletion effect causing V/sub th/ shift, a higher /spl sigma//sub Vth/, and higher Vth mismatch. Thus, attention to this detrimental trench isolation step-induced (TRISI) narrow width effect is essential for scaled isolation design.     

Two-dimensional analysis of triode-like operation of junction gate FET's

Triode-like operation of junction gate FET's is analyzed by two-dimensional computer simulation. Triode-like characteristics are shown to appear with the channel normally off and the depletion layer reaching the drain electrode. Triode-like current arises from carrier injection from the source electrode into the depleted region. Triode-like operation is achieved without intrinsic material.     

Two-dimensional numerical analysis of floating-gate EEPROM devices

The importance of transient analysis in the design of floating-gate EEPROMs is demonstrated. Anomalous behavior, which was identified during transient measurements, has been simulated using HFIELDS, a general-purpose two-dimensional (2D) numerical device simulator. The corrective action that was taken at the time to eliminate the problem has been analyzed and explained using the simulation results. In addition, the simulator has been used to investigate 2D effects in the device due to process nonidealities     

Two-dimensional numerical analysis of the high electron mobility transistor

We develop a two-dimensional model for the high electron mobility transistor (HEMT) including conduction outside the quantum well. The model uses the continuity and power balance moment equations for both inside and outside the well, with electron concentration and average energy as dependent variables, and with parameters determined by Monte Carlo simulation. We show that conduction outside the well is dominant in the "pinchoff" region and that consequently the speed advantage of the HEMT over conventional devices does not arise from high saturation velocities in the quantum well but rather from a lower access resistance as suggested by a velocity profile calculation. It is further demonstrated that several effects which are unimportant in conventional FET's are of significance in the HEMT. Among these effects are electronic heat conduction and to some extent real space transfer.     

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.     

Zero gate leakage current in the enhancement mode MOSFET

Gate leakage current measurements of the enhancement mode MOSFET taken with a vibrating reed electrometer in a carefully controlled environment indicate that zero gate leakage current can be achieved. The zero region is delineated by the change of sign in the gate leakage current when the drain-to-source voltage is increased.     

Two-dimensional numerical analysis of impurity atom diffusion in semiconductors

Linear two-dimensional diffusion of impurity atom through finite-dimension masks has been numerically examined. Numerical simulation results demonstrate the limits of the two-dimensional analytical diffusion model which was first employed in the well-known paper by Kennedy and O'Brien [1].     

New observation of gate current in off-state MOSFET

For a gate-controlled p⁺-n diode having gate-p⁺ overlap area of 3.7×10^-4 cm², the author reports a new observation of the leakage currents through a 235-Å gate oxide. The gate current components both due to Fowler-Nordheim electron funneling through the gate-p⁺ overlap oxide and due to hot-electron injections were separately detected. The corresponding gate current was found to be dominated by Fowler-Nordheim electron funneling prior to significant surface avalanche impact ionization     

Nondestructive determination of MOSFET gate breakdown voltage

A method is presented which allows the gate breakdown of a MOSFET to be nondestructively determined. The method applies a linear ramp voltage across the gate, allowing the leakage component to be easily separated from the capacitive currents. In this manner, the leakage component can be measured before it becomes large enough to cause a destructive dielectric breakdown in the gate oxide.     

Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations

In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in the determination of the drain current of short-channel MOSFET's by way of analytical expressions. The validity of these published expressions has not been verified so far for small-geometry devices of different parameters. Further, the relationship between the threshold voltage shift and the barrier lowering due to the DIBL effect has not been clarified in the literature. In our present paper we carried a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and subthreshold current. Further, we found that the calculated DIBL parameters of the analytical model reported in the literature do not agree with the numerically computed values. Hence we determined a set of new geometry parameters η andB/Afor the DIBL threshold relationship that can be used with the analytical model. Our work stresses the necessity of the use of two-dimensional numerical simulations when accurate evaluation of the DIBL effect in short-channel MOSFET's is required. Also, our results should be useful for calibrating existing analytical MOSFET models. In addition, our data and method could be used as a design tool for performance optimization of micrometer and submicrometer devices.