Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

适用于数据通路的可编程逻辑器件FDP100K

设计研制了一款适用于数据通路的10万门容量的FPGA器件FDP100K(FDP:FPGA for Data-Path),其主要特点为:可编程逻辑单元结构不同于国际上已有的可编程逻辑单元结构,是一种新颖的基于查询表LUT和多路选择器MUX的混合结构;连线资源结构采用新颖的层次式布线结构,提供高度灵活的布线能力.芯片采用SMIC 0.35 μm CMOS工艺,包含1024个可编程逻辑单元和128个可编程IO单元.芯片配合自主开发的软件系统FDE(FPGA Development Environment)进行测试,结果表明:FDP100K芯片的可编程逻辑单元功能正常;芯片的各种连线资源功能正常;可以准确地实现数据通路型电路和其他类型的电路的功能.     

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays

Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, “finite” wire length, and a discrete number of repeaters. A metric introduced during the design is the “path delay profile”, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the “path delay profile” arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.

基于FPGA实现随机逻辑的混合不确定性故障树分析研究

文中提出一种基于随机逻辑的故障树分析方法,即使用混合故障树分析(HFTA)来兼顾客观不确定性和主观不确定性。该方法将每个故障树逻辑门转换为其对应的随机逻辑模块,然后在现场可编程门阵列(FPGA)中实现。随后在a截集置信度水平等于0的情况下比较常规方法和本文方法的精度和性能。分析结果表明,相较于常规混合不确定性分析方法,文中提出的方法缩短了分析时间。由于与常规混合方法的顶事件概率累积分布函数基本相容,可以认为新方法与常规混合方法的结果精度基本一致。     

PLBMAP:高性能通用FPGA可编程逻辑块映射算法

研究了一种低复杂度、高利用率、高性能的通用FPGA逻辑块映射算法,基本思想包括为降低算法复杂度而提出的将组合电路与时序电路分开映射、对逻辑单元分层;引入匹配度系数以提高逻辑单元的利用率,从而在算法的性能和速度两方面均得到了较好的突破:平均性能比现存通用映射算法提高了12.59%,平均运行时间可以降低102～103倍.     

激光测高仪中基于现场可编程门阵列的高精度飞行时间测量

设计了在激光测高系统中基于单芯片现场可编程门阵列(FPGA)的高精度时间间隔测量模块。该模块采用高频计数器实现粗时间测量,差分延时线内插技术完成细时间测量,时间分辨率为300 ps。该芯片同时还集成了时序切割电路、回波脉宽测量和数据传输模块等。在环境温度20℃时对该测量模块进行精度测试,获得标准偏差为94.68 ps,转换成距离为1.42 cm。最后通过地面检测,整个系统在500 km范围内的一般条件下可获得测高精度±50 cm。     

基于测试系统的FPGA逻辑资源的测试

FPGA在许多领域已经得到广泛应用,其测试问题也显得越来越突出。文章针对基于SRAM结构FPGA的特点,以Xilinx公司的XC4000系列芯片为例,利用检测可编程逻辑资源的多逻辑单元(CLB)混合故障的测试方法,阐述了如何在BC3192V50测试系统上实现FPGA的在线配置以及功能和参数测试。它是一种基于测试系统的通用的FPGA配置和测试方法。     

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.     

Combined probabilistic testability calculation and compact test generation for PLAs

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved.¹ This work was done while B. Reppen was with the Norwegian Institute of Technology.     

Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array

In this paper, analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex（OFDM） system, and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms. Based on the analysis of coarse and elaborate synchronization algorithms, multiplexed are, the module accumulator, division and output judgement, which can evidently save the hardware resource cost. The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption.     

Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation

The polyphase filter approach to quadrature demodulation is shown to be well suited for the implementation of purpose-designed wide bandwidth digital quadrature demodulators. The duplicated polyphase filter approach is introduced, as a way to increase the maximum allowable input signal bandwidth for a given implementation technology. Other algorithmic and architectural considerations specifically applicable to the realization of digital filters in low-cost Field-Programmable Gate Array (FPGA) technology are discussed. A design example suitable for processing input signals centered on an intermediate frequency of 160 MHz with a bandwidth of 45 MHz is presented. This design occupies 83% of the Configurable Logic Blocks (CLBs) in a low-cost Xilinx X4010E-3 FPGA. Additional techniques for further performance optimization are presented.     

FPGA准实时寿命损耗评价系统的验证试验设计

为验证已建立的现场可编程门阵列(FPGA)器件准实时寿命评价系统的工程合理性,进行了加速寿命试验的设计.验证试验的设计,考虑不同型号之间的可靠性差异,针对特定型号的Xilinx XCV600 FPGA样本,能够定位样本内部具体失效部位.针对FPGA高可靠性的特点,施加温度、电压和频率3种加速应力;针对FPGA使用环境多变的特点,构建了整套载荷数据跟踪与处理流程.试验方案通过硬件和软件系统实现,硬件系统进行FPGA工作环境的加载及准实时工作情况数据的采集,软件系统基于电迁移失效机理对采集到的数据进行处理得到寿命信息,将试验与预测结果进行比对完成验证.实践表明了该试验设计的可实施性,确认了部分系统预测结果的准确性.     

A Full Coverage Test Method for Configurable Logic Blocks in FPGA

FPGA＇s conflgurability makes it difficult for FPGA＇s manufacturers to fully test it. In this paper, a full coverage test method for FPGA＇s Conflgurable logic blocks （CLBs） is proposed, through which all basic logics of FPGA＇s every CLB can be fully tested. Innovative test circuits are designed using FPGA＇s internal resources to build Iterative logic arrays （ILAs） for Look-up tables （LUTs）, distributed random access memories, configurable registers and other logics. The programmable interconnects needed to connect CLBs in these test circuits are also repeatable, making the configuration process much easier and the test speed much faster. The test method is transplantable and independent of FPGA＇s array size, so it can be applied to the test of different FPGAs. Xilinx＇s Virtex FPGA is taken as an example to explain our method, where only 19 test configurations are needed to achieve 100% coverage for all CLBs. To evaluate the test method reliably and guide the process of test vectors generation, a fault simulator- Turbofault is used to simulate FPGA＇s test coverage.     

手持式微机械陀螺扫频测试仪的实现

传统微机械陀螺的扫频测试一般采用价格昂贵的通用测试仪,其存在测试成本高、效率低等缺点。设计了一种基于现场可编程门阵列(FPGA)的手持扫频测试仪,能够自动进行扫频测试并求取被测微机械陀螺的谐振频率与品质因数,通过手动调节直流偏置电压大小的方式进行直流扫频测试,在自身的显示屏上绘制相关特性曲线。采用直接数字合成技术产生交流驱动信号,利用最小二乘拟合算法快速定位谐振频率点的大致位置,可以缩短测试时间、提高测试效率。应用测试表明,手持式微机械陀螺扫频测试仪能够快速、准确地完成微机械陀螺扫频测试,测试结果与传统测试方式吻合很好。     

DSP处理器单粒子翻转率测试系统的研制

航天器及其内部元器件在太空中会受到单粒子效应(SEE)带来的威胁,因此航天用电子器件在装备前必须进行抗SEE能力的测试评估。针对传统测试方法存在的测试系统程序容易在辐照过程崩溃、统计翻转数不准确、单粒子闩锁(SEL)辨别不清晰和忽略内核翻转统计等问题,设计了一种测试系统,通过片外加载与运行程序从而减少因辐照导致片内程序异常的现象;通过片外主控电路统计被测电路翻转数使统计翻转结果准确;通过主控电路控制被测电路时钟供给排除因频率增加导致电流过大而误判发生SEL的情况;通过内核指令集统计内核翻转数。实验结果表明,该测试系统可以实时全面地监测数字信号处理器(DSP)的SEE,并有效防止辐照实验器件(DUT)因SEL而失效。     

应用于辐照实验的通用CCD测试电路设计

电荷耦合器件(CCD)辐射效应测试系统需具备通用性。通常情况下需要为每一种CCD设计一款测试电路,无法满足通用性要求,通用性电路的难点在于不同CCD要求不同的驱动通道数、驱动时序、信号占空比及工作点。提出了一种适用于多种CCD的测试电路设计方法。以现场可编程门阵列(FPGA)负责时序发生、工作点调节及整个系统的控制,驱动模块采用工作点可调的模式,并结合电荷泵技术,仅需更改FPGA设计及给驱动模块提供不同的工作点电压,便可使以上驱动参数可调,实现测试电路的通用性。采用该方法进行测试还可以适应CCD辐照后工作点的变化。最后通过正确驱动TCD1209线阵CCD和4096×96型TDI-CCD,并对TDI-CCD总剂量辐照实验进行正确的参数测试,验证了通用测试电路设计方法的可行性。