A lateral silicon-on-insulator bipolar transistor with a self-aligned base contact

A novel lateral bipolar transistor structure in silicon-on-insulator (SOI) is presented. The structure allows for a minimum geometry base width yet still provides for a metal contact to the entire base region. Fabricated transistors exhibit a base resistance of less than 20 Ω.     

Current gain of silicon bipolar transistor with polysilicon emitter contact

A two-region analysis is presented to predict the common-emitter current gain of a bipolar transistor with the polysilicon contact to the emitter for a case when the recombinations at the mono-poly interface are not negligible. The calculated current-gain enhancement for typical device parameters and for different values of interface recombination velocity show that the current-gain enhancement and its increase with decrease of emitter width is smaller for the interface with larger recombinations.     

New de-embedding method for millimetre-wave bipolar transistor S-parameter measurement

An improved de-embedding method is used to measure the intrinsic HBT S parameters to millimetre wave frequencies. Standard twelve-error element models and dummy pads with resistors as calibration standards are used. This new method correctly reveals the effect from the extra delay time, parasitic capacitance, and parasitic inductance introduced by the layout and enables the performance at millimetre-wave frequencies to be accurately predicted.<>     

A simple method of bipolar transistor field factor measurement

A method of bipolar transistor field factor measurement is described. The method is based on the measurement of the open-circuit voltage between the collector-base terminals when a forward bias voltage is applied across the emitter-base terminals. The theory and the experimental measurement on different transistor types are presented.     

A high-conductivity insulated gate bipolar transistor with Schottky hole barrier contact

This letter proposes a high-conductivity insulated gate bipolar transistor (HC-IGBT) with Schottky contact formed on the p-base, which forms a hole barrier at the p-base side to enhance the conductivity modulation effect. TCAD simulation shows that the HC-IGBT provides a current density increase by 53% and turn-off losses decrease by 27% when compared to a conventional field-stop IGBT (FS-IGBT). Hence, the proposed IGBT exhibits superior electrical performance for high-efficiency power electronic systems.     

Thin-base bipolar transistor fabrication using gas immersion laserdoping

Gas immersion laser doping (GILD) is used to fabricate the base and emitter regions of narrow-base n-p-n bipolar transistors. The GILD process is unique in that it allows simple fabrication of box-like impurity profiles which can be placed very accurately in the vertical dimension (±100 Å). Transistors with base widths ranging from 700 to 1200 Å and DC forward current gains greater than 50 are fabricated     

Direct measurement of field transistor threshold voltages using inversion layer fed transistors in deep submicron processes

Polysilicon field transistors are traditionally overlapped onto thin-oxide regions to connect to the source and drain of a transistor. Submicron processes have gate oxides with breakdown voltages below the field threshold and the traditional layout is not suitable. It is, however, necessary to maintain a channel to the source and drain, but this can be accomplished using a field plate device. By placing a metal gate over the poly gate, and biasing the metal gate into strong inversion, it is possible for the polysilicon gate to control the transistor current. In fact with this one structure both the polysilicon and metal-field threshold voltages can be ascertained.     

An advanced physics-based sub-circuit model of a punch-trough insulated gate bipolar transistor

An advanced sub-circuit model of the punch-trough insulated gate bipolar transistor (PT IGBT) based on the physics of internal device operation has been described in this article. The one-dimensional physical model of low-gain wide-base BJT is employed based on the equivalent non-linear lossy transmission line, whereas a SPICE Level 3 model is used for the diffused MOST part. The influence of voltage dependent drain-to-gate overlapping capacitance and the conductivity modulated base (drain) ohmic resistance are modelled separately. The main advantages of novel PT IGBT model are a small set of model parameters, an easy implementation in SPICE simulator and the high accuracy confirmed by comparing the simulation results with the electrical measurements of test power circuit.     

An advanced bipolar transistor with self-aligned ion-planted baseand W/poly emitter

The fabrication, device profile, and electrical characteristics of an advanced bipolar transistor with an LDD-like self-aligned lateral profile are discussed. An ion-implanted extrinsic base with a low sheet resistance of 55 Ω/square and a junction depth of 0.35 μm is obtained using rapid thermal annealing. The extrinsic base and emitter are separated by a temporary submicrometer sidewall spacer, which is subsequently removed to maintain a planar surface during the emitter-active-base formation process. The emitter is contacted by a W-TiN-n⁺ polysilicon stack with a sheet resistance of 1 Ω/square. As a result of the planarity of the surface during the profile formation for the active region and the decoupling of the structural process from the thin base process, an active base width of 105 nm is obtained     

Electrical characteristics of advanced lateral insulated-gate bipolar transistor structures at 77 K

The electrical characteristics of advanced 360 V lateral insulated-gate bipolar transistor (LIGBT) structures operating at cryogenic temperatures are analysed in this paper. Detailed performed static and dynamic measurements on ceramic packaged LIGBT structures at 77 K are provided. A reduction of the breakdown voltage, the leakage current, the turn-off time and the transient losses has been observed when decreasing the operating temperature. A reduction of 70% of the turn-off time and a 45% of switching losses can be obtained when lowering the temperature from 300 to 77 K. At high current density levels, the on-state voltage drop of the conventional LIGBT structure increases with temperature. On the contrary, on-state voltage drop of an advanced modified LIGBT structure increases when the temperature is reduced.     

Recent progress in bipolar transistor technology

Recent developments in high speed silicon bipolar device technologies are reviewed. Bipolar device structures that include polysilicon are key technologies for improving circuit characteristics. Double polysilicon bipolar device structures, in particular, have made it possible both to form shallow junctions and to reduce device dimensions. Recent progress of silicon bipolar transistor technology using SiGe and the use of the SOI technology to obtain high speed operations are also reviewed     

Distortion in bipolar transistor variable-gain amplifiers

Wide-band variable-gain amplifiers consisting of bipolar junction transistors and exhibiting maximum gain larger than unity are considered. The mechanisms of distortion are analyzed at low and high frequencies. Approximate expressions for distortion are derived and give good agreement with computational results and measurements. The most common high-performance variable-gain circuit realizations are discussed and compared for distortion performance.     

Reduced contact resistance and highly stable operation in polymer thin-film transistor with aqueous MoOx solution contact treatment

We report on a newly developed solution process using MoO₃ for reducing source and drain (S/D) electrodes in organic thin-film transistor (TFT). By taking advantage of the difference in surface wettability between the gate dielectric layer and the S/D electrodes, the electrode treatment using the MoO_x solution was applied to polymer TFT with short channel lengths less than 10 μm. The contact resistance was noticeably reduced at the interface of the S/D electrodes in a polymer TFT using a pBTTT-C16. Furthermore, the field effect mobility for this TFT was enhanced from 0.03 to 0.1 cm²/V s. Most notably, the threshold voltage (V_th) shift under gated bias stress was less than 0.2 V after 10⁵ s, which is comparable to that of conventional poly crystalline Si TFT.     

A direct measurement of interfacial contact resistance

A method is described for directly measuring interfacial contact resistance and estimating the degree of uniformity of the interfacial layer in metal-semiconductor contacts. A two-dimensional resistor network model is used to obtain a relationship between the specific contact resistance and the measured interfacial contact resistance for contacts with a homogeneous interfacial layer. Measurement results are given for 98.5% Al/1.5% Si and 100 % Al contacts on n-type silicon.     

An uncompensated silicon bipolar junction transistor fabricated using molecular beam epitaxy

The first silicon bipolar junction transistor fabricated using molecular beam epitaxy is reported. Epitaxial layers defining the collector, base, and emitter regions are grown successively at 850°C. Because no thermal diffusion steps are involved, junction location and base width are precisely defined. The final structure is mesa isolated using reactive ion etching. A peak forward current gain of 60 is measured. This technique is expected to be applicable to the development of very narrow base, ultrahigh speed bipolar transistors.     

A high-density MOS static RAM cell using the lambda bipolar transistor

Based upon the common-collector lambda bipolar transistor (LBT), which is built with p-well NMOS, and the parasitic n-p-n BJT in a CMOS IC, a novel MOS static RAM cell called the LBT cell is proposed. In this new cell, the LBT and two poly-Si resistors form a bistable element with a PMOS access transistor. With the minimum feature size F, the optimal cell area of 32 F/SUP 2/ can be realized by using the silicide contact and small p-well spacing. The READ-WRITE operation is simulated. Due to the need of precharging before reading and the rather slow recovery after reading, suitable peripheral circuits should be designed.     

Quasi-dielectrically isolated bipolar junction transistor withsubcollector fabricated using silicon selective epitaxy

A novel quasi-dielectrically isolated bipolar junction transistor (QDI-BJT) was developed for intelligent power ICs. Using a combination of junction and dielectric isolation, the QDI-BJT was achieved by selective epitaxial growth (SEG) of single-crystal silicon in an oxide-lined trench. Buried collectors formed by ion implantation and in situ doped SEG silicon drastically reduce collector resistance with no detrimental effects on transistor performance. The emitter-base and collector-base ideality factors at 1.10 and 1.09, respectively, were very close to those of similar devices fabricated in the substrate in the same die, indicating excellent crystal quality of the SEG silicon. Due to the use of a trench structure to facilitate isolation and control the SEG thickness, the QDI process can be used for any application where the thickness and resistivity of the control and power areas are independently optimized     

Ultra-thin-base Si bipolar transistor using rapid vapor-phasedirect doping (RVD)

A novel doping method called rapid vapor-phase direct doping (RVD) is developed to form ultra-shallow junctions. The base region of a conventional bipolar transistor is formed by this method, and in ultra-narrow 25-nm base is obtained. The Gummel plot of this device shows almost ideal characteristics. This result suggests that this method does not induce any defects which cause a leakage current. RVD is a thermal diffusion method using hydrogen as a carrier gas and B₂ H₆ as a source gas. In this method, the impurity atoms directly diffuse from the vapor phase into silicon by a rapid thermal process without a boron-glass layer or metallic boron layer. By varying the source gas flow rate, doping time, and temperature, ultra-shallow junctions below 40 nm with controlled surface concentrations are successfully formed. An ultra-shallow 20-nm junction with surface boron concentration of 4×10¹⁸ cm^-3 is obtained at 800°C for 5 min with B₂H₆ flow rate of 30 ml/min     

An advanced PNP bipolar transistor design for a low-power and very-high-performance quarter-micron CBiCMOS process

This paper describes an advanced PNP bipolar transistor which has been designed by using the mixed two-dimensional device/circuit simulation (CODECS) [1] for a low-power and very-high-performance 0.25 μm complementary BiCMOS (CBiCMOS) device. The optimized PNP structure has a 30-nm-wide emitter, a 39-nm-wide intrinsic base region, a maximum cut-off frequency of 14 GHz and a current gain of 16 (without poly-Si emitter effect). A high performance and limits in terms of delay for pull-down of 0.25 μm CBiCMOS were obtained and compared to those offered by BiCMOS and complementary metal-oxide semiconductor circuits at different power supplies and charge capacitance. An improvement of 1.5 × at 1 pF, 1.6 × at 0.6 pF and 2 × at 0.2 pF over BiCMOS has been achieved.