Transition Metal Dichalcogenide‐Based Transistor Circuits for Gray Scale Organic Light‐Emitting Displays

Two types of transition metal dichalcogenide (TMD) transistors are applied to demonstrate their possibility as switching/driving elements for the pixel of organic light‐emitting diode (OLED) display. Such TMD materials are 6 nm thin WSe₂ and MoS₂ as a p‐type and n‐type channel, respectively, and the pixel is thus composed of external green OLED and nanoscale thin channel field effect transistors (FETs) for switching and driving. The maximum mobility of WSe₂‐FETs either as switch or as driver is ≈30 cm² V^?1 s^?1, in linear regime of the gate voltage sweep range. Digital (ON/OFF‐switching) and gray‐scale analogue operations of OLED pixel are nicely demonstrated. MoS₂ nanosheet FET‐based pixel is also demonstrated, although limited to alternating gray scale operation of OLED. Device stability issue is still remaining for future study but TMD channel FETs are very promising and novel for their applications to OLED pixel because of their high mobility and I _D ON/OFF ratio.     

Implementation of Low‐Power Electronic Devices Using Solution‐Processed Tantalum Pentoxide Dielectric

The development of solution‐processed field effect transistors (FETs) based on organic and hybrid materials over the past two decades has demonstrated the incredible potential in these technologies. However, solution processed FETs generally require impracticably high voltages to switch on and off, which precludes their application in low‐power devices and prevent their integration with standard logic circuitry. Here, a universal and environmentally benign solution‐processing method for the preparation of Ta₂O₅, HfO₂ and ZrO₂ amorphous dielectric thin films is demonstrated. High mobility CdS FETs are fabricated on such high‐κ dielectric substrates entirely via solution‐processing. The highest mobility, 2.97 cm² V^?1 s^?1 is achieved in the device with Ta₂O₅ dielectric with a low threshold voltage of 1.00 V, which is higher than the mobility of the reference CdS FET with SiO₂ dielectric with an order of magnitude decrease in threshold voltage as well. Because these FETs can be operated at less than 5 V, they may potentially be integrated with existing logic and display circuitry without significant signal amplification. This report demonstrates high‐mobility FETs using solution‐processed Ta₂O₅ dielectrics with drastically reduced power consumption; ≈95% reduction compared to that of the device with a conventional SiO₂ gate dielectric.     

Non‐Lithographic Fabrication of All‐2D α‐MoTe2 Dual Gate Transistors

As one of the emerging new transition‐metal dichalcogenides materials, molybdenum ditelluride (α‐MoTe₂) is attracting much attention due to its optical and electrical properties. This study fabricates all‐2D MoTe₂‐based field effect transistors (FETs) on glass, using thin hexagonal boron nitride and thin graphene in consideration of good dielectric/channel interface and source/drain contacts, respectively. Distinguished from previous works, in this study, all 2D FETs with α‐MoTe₂ nanoflakes are dual‐gated for driving higher current. Moreover, for the present 2D dual gate FET fabrications on glass, all thermal annealing and lithography processes are intentionally exempted for fully non‐lithographic method using only van der Waal's forces. The dual‐gate MoTe₂ FET displays quite a high hole and electron mobility over ≈20 cm² V^?1 s^?1 along with ON/OFF ratio of ≈10⁵ in maximum as an ambipolar FET and also demonstrates high drain current of a few tens‐to‐hundred μA at a low operation voltage. It appears promising enough to drive organic light emitting diode pixels and NOR logic functions on glass.     

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS2 Field‐Effect Transistors

2D materials are promising to overcome the scaling limit of Si field‐effect transistors (FETs). However, the insulator/2D channel interface severely degrades the performance of 2D FETs, and the origin of the degradation remains largely unexplored. Here, the full energy spectra of the interface state densities (D_it) are presented for both n‐ and p‐ MoS₂ FETs, based on the comprehensive and systematic studies, i.e., full rage of channel thickness and various gate stack structures with h‐BN as well as high‐k oxides. For n‐MoS₂, D_it around the mid‐gap is drastically reduced to 5 × 10¹¹ cm^?2 eV^?1 for the heterostructure FET with h‐BN from 5 × 10¹² cm^?2 eV^?1 for the high‐k top‐gate. On the other hand, D_it remains high, ≈ 10¹³ cm^?2 eV^?1, even for the heterostructure FET for p‐MoS₂. The systematic study elucidates that the strain induced externally through the substrate surface roughness and high‐k deposition process is the origin for the interface degradation on conduction band side, while sulfur‐vacancy‐induced defect states dominate the interface degradation on valance band side. The present understanding of the interface properties provides the key to further improving the performance of 2D FETs.     

High‐Mobility ZnO Thin Film Transistors Based on Solution‐processed Hafnium Oxide Gate Dielectrics

The properties of metal oxides with high dielectric constant (k) are being extensively studied for use as gate dielectric alternatives to silicon dioxide (SiO₂). Despite their attractive properties, these high‐k dielectrics are usually manufactured using costly vacuum‐based techniques. In that respect, recent research has been focused on the development of alternative deposition methods based on solution‐processable metal oxides. Here, the application of the spray pyrolysis (SP) technique for processing high‐quality hafnium oxide (HfO₂) gate dielectrics and their implementation in thin film transistors employing spray‐coated zinc oxide (ZnO) semiconducting channels are reported. The films are studied by means of admittance spectroscopy, atomic force microscopy, X‐ray diffraction, UV–Visible absorption spectroscopy, FTIR, spectroscopic ellipsometry, and field‐effect measurements. Analyses reveal polycrystalline HfO₂ layers of monoclinic structure that exhibit wide band gap (≈5.7 eV), low roughness (≈0.8 nm), high dielectric constant (k ≈ 18.8), and high breakdown voltage (≈2.7 MV/cm). Thin film transistors based on HfO₂/ZnO stacks exhibit excellent electron transport characteristics with low operating voltages (≈6 V), high on/off current modulation ratio (～10⁷) and electron mobility in excess of 40 cm² V^?1 s^?1.     

High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

Organic Electronics: High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment (Adv. Funct. Mater. 16/2010)

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

Fully Transparent p‐MoTe2 2D Transistors Using Ultrathin MoOx/Pt Contact Media for Indium‐Tin‐Oxide Source/Drain

Since transition metal dichalcogenide (TMD) semiconductors are found as 2D van der Waals materials with a discrete energy bandgap, many 2D‐like thin field effect transistors (FETs) and PN diodes are reported as prototype electrical and optoelectronic devices. As a potential application of display electronics, transparent 2D FET devices are also reported recently. Such transparent 2D FETs are very few in report, yet no p‐type channel 2D‐like FETs are seen. Here, 2D‐like thin transparent p‐channel MoTe₂ FETs with oxygen (O₂) plasma‐induced MoO_x/Pt/indium‐tin‐oxide (ITO) contact are reported for the first time. For source/drain contact, 60 s short O₂ plasma and ultrathin Pt‐deposition processes on MoTe₂ surface are sequentially introduced before ITO thin film deposition and patterning. As a result, almost transparent 2D FETs are obtained with a decent mobility of ≈5 cm² V^?1 s^?1, a high ON/OFF current ratio of ≈10⁵, and 70% transmittance. In particular, for normal MoTe₂ FETs without ITO, O₂ plasma process greatly improves the hole injection efficiency and device mobility (≈60 cm² V^?1 s^?1), introducing ultrathin MoO_x between Pt source/drain and MoTe₂. As a final device application, a photovoltaic current modulator, where the transparent FET stably operates as gated by photovoltaic effects, is integrated.     

High Performance Multi‐Level Non‐Volatile Polymer Memory with Solution‐Blended Ferroelectric Polymer/High‐k Insulators for Low Voltage Operation

Polymer ferroelectric‐gate field effect transistors (Fe‐FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next‐generation non‐volatile memory. Furthermore, polymer Fe‐FETs have been recently of interest owing to their capability of storing data in more than 2 states in a single device, that is, they have multi‐level cell (MLC) operation potential for high density data storage. However, among a variety of technological issues of MLC polymer Fe‐FETs, the requirement of high voltage for cell operation is one of the most urgent problems. Here, a low voltage operating MLC polymer Fe‐FET memory with a high dielectric constant (k) ferroelectric polymer insulator is presented. Effective enhancement of capacitance of the ferroelectric gate insulator layer is achieved by a simple binary solution‐blend of a ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (PVDF‐TrFE) (k ≈ 8) with a relaxer high‐k poly(vinylidene‐fluoride–trifluoroethylene–chlorotrifluoroethylene) (PVDF‐TrFE‐CTFE) (k ≈ 18). At optimized conditions, a ferroelectric insulator with a PVDF‐TrFE/PVDF‐TrFE‐CTFE (10/5) blend composition enables the discrete six‐level multi‐state operation of a MLC Fe‐FET at a gate voltage sweep of ±18 V with excellent data retention and endurance of each state of more than 10⁴ s and 120 cycles, respectively.     

Low Voltage and Ferroelectric 2D Electron Devices Using Lead‐Free BaxSr1‐xTiO3 and MoS2 Channel

Coupling between non‐toxic lead‐free high‐k materials and 2D semiconductors is achieved to develop low voltage field effect transistors (FETs) and ferroelectric non‐volatile memory transistors as well. In fact, low voltage switching ferroelectric memory devices are extremely rare in 2D electronics. Now, both low voltage operation and ferroelectric memory function have been successfully demonstrated in 2D‐like thin MoS₂ channel FET with lead‐free high‐k dielectric Ba_xSr_1‐xTiO₃ (BST) oxides. When the BST surface is coated with a 5.5‐nm‐ultrathin poly(methyl methacrylate) (PMMA)‐brush for improved roughness, the MoS₂ FET with BST (x = 0.5) dielectric results in an extremely low voltage operation at 0.5 V. Moreover, the BST with an increased Ba composition (x = 0.8) induces quite good ferroelectric memory properties despite the existence of the ultrathin PMMA layer, well switching the MoS₂ FET channel states in a non‐volatile manner with a ±3 V low voltage pulse. Since the employed high‐k dielectric and ferroelectric oxides are lead‐free in particular, the approaches for applying high‐k BST gate oxide for 2D MoS₂ FET are not only novel but also practical towards future low voltage nanoelectronics and green technology.     

Water‐Induced Scandium Oxide Dielectric for Low‐Operating Voltage n‐ and p‐Type Metal‐Oxide Thin‐Film Transistors

Solution‐processed metal‐oxide thin films based on high dielectric constant (k) materials have been extensively studied for use in low‐cost and high‐performance thin‐film transistors (TFTs). Here, scandium oxide (ScO_x) is fabricated as a TFT dielectric with excellent electrical properties using a novel water‐inducement method. The thin films are annealed at various temperatures and characterized by using X‐ray diffraction, atomic‐force microscopy, X‐ray photoelectron spectroscopy, optical spectroscopy, and a series of electrical measurements. The optimized ScO_x thin film exhibits a low‐leakage current density of 0.2 nA cm^?2 at 2 MV cm^?1, a large areal capacitance of 460 nF cm^?2 at 20 Hz and a permittivity of 12.1. To verify the possible applications of ScO_x thin films as the gate dielectric in complementary metal oxide semiconductor (CMOS) electronics, they were integrated in both n‐type InZnO (IZO) and p‐type CuO TFTs for testing. The water‐induced full oxide IZO/ScO_x TFTs exhibit an excellent performance, including a high electron mobility of 27.7 cm² V^?1 s^?1, a large current ratio (I_on/I_off) of 2.7 × 10⁷ and high stability. Moreover, as far as we know it is the first time that solution‐processed p‐type oxide TFTs based on a high‐k dielectric are achieved. The as‐fabricated p‐type CuO/ScO_x TFTs exhibit a large I_on/I_off of around 10⁵ and a hole mobility of 0.8 cm² V^?1 at an operating voltage of 3 V. To the best of our knowledge, these electrical parameters are among the highest performances for solution‐processed p‐type TFTs, which represents a great step towards the achievement of low‐cost, all‐oxide, and low‐power consumption CMOS logics.     

A High‐k Fluorinated P(VDF‐TrFE)‐g‐PMMA Gate Dielectric for High‐Performance Flexible Field‐Effect Transistors

A newly synthesized high‐k polymeric insulator for use as gate dielectric layer for organic field‐effect transistors (OFETs) obtained by grafting poly(methyl methacrylate) (PMMA) in poly(vinylidene fluoride‐trifluoroethylene) (P(VDF‐TrFE)) via atom transfer radical polymerization transfer is reported. This material design concept intents to tune the electrical properties of the gate insulating layer (capacitance, leakage current, breakdown voltage, and operational stability) of the high‐k fluorinated polymer dielectric without a large increase in operating voltage by incorporating an amorphous PMMA as an insulator. By controlling the grafted PMMA percentage, an optimized P(VDF‐TrFE)‐g‐PMMA with 7 mol% grafted PMMA showing reasonably high capacitance (23–30 nF cm^?2) with low voltage operation and negligible current hysteresis is achieved. High‐performance low‐voltage‐operated top‐gate/bottom‐contact OFETs with widely used high mobility polymer semiconductors, poly[[2,5‐bis(2‐octyldodecyl)‐2,3,5,6‐tetrahydro‐3,6‐dioxopyrrolo [3,4‐c]pyrrole‐1,4‐diyl]‐alt‐[[2,2′‐(2,5‐thiophene)bis‐thieno(3,2‐b)thiophene]‐5,5′‐diyl]] (DPPT‐TT), and poly([N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)) are demonstrated here. DPPT‐TT OFETs with P(VDF‐TrFE)‐g‐PMMA gate dielectrics exhibit a reasonably high field‐effect mobility of over 1 cm² V^?1 s^?1 with excellent operational stability.     

High‐Mobility and Low Turn‐On Voltage n‐Channel OTFTs Based on a Solution‐Processable Derivative of Naphthalene Bisimide

In organic electronics solution‐processable n‐channel field‐effect transistors (FETs) matching the parameters of the best p‐channel FETs are needed. Progress toward the fabrication of such devices is strongly impeded by a limited number of suitable organic semiconductors as well as by the lack of processing techniques that enable strict control of the supramolecular organization in the deposited layer. Here, the use of N,N′‐bis(4‐n‐butylphenyl)‐1,4,5,8‐naphthalenetetracarboxylic‐1,4:5,8‐bisimide (NBI‐4‐n‐BuPh) for fabrication of n‐channel FETs is described. The unidirectionally oriented crystalline layers of NBI‐4‐n‐BuPh are obtained by the zone‐casting method under ambient conditions. Due to the bottom‐contact, top‐gate configuration used, the gate dielectric, Parylene C, also acts as a protective layer. This, together with a sufficiently low LUMO level of NBI‐4‐n‐BuPh allows the fabrication and operation of these novel n‐channel transistors under ambient conditions. The high order of the NBI‐4‐n‐BuPh molecules in the zone‐cast layer and high purity of the gate dielectric yield good performance of the transistors.     

High‐Mobility Air‐Stable Naphthalene Diimide‐Based Copolymer Containing Extended π‐Conjugation for n‐Channel Organic Field Effect Transistors

A high‐performance naphthalene diimide (NDI)‐based conjugated polymer for use as the active layer of n‐channel organic field‐effect transistors (OFETs) is reported. The solution‐processable n‐channel polymer is systematically designed and synthesized with an alternating structure of long alkyl substituted‐NDI and thienylene–vinylene–thienylene units (PNDI‐TVT). The material has a well‐controlled molecular structure with an extended π‐conjugated backbone, with no increase in the LUMO level, achieving a high mobility and highly ambient stable n‐type OFET. The top‐gate, bottom‐contact device shows remarkably high electron charge‐carrier mobility of up to 1.8 cm² V^?1 s^?1 (I_on/I_off = 10⁶) with the commonly used polymer dielectric, poly(methyl methacrylate) (PMMA). Moreover, PNDI‐TVT OFETs exhibit excellent air and operation stability. Such high device performance is attributed to improved π–π intermolecular interactions owing to the extended π‐conjugation, apart from the improved crystallinity and highly interdigitated lamellar structure caused by the extended π–π backbone and long alkyl groups.     

Variable Temperature Mobility Analysis of n‐Channel,p‐Channel,and Ambipolar Organic Field‐Effect Transistors

The temperature dependence of field‐effect transistor (FET) mobility is analyzed for a series of n‐channel, p‐channel, and ambipolar organic semiconductor‐based FETs selected for varied semiconductor structural and device characteristics. The materials (and dominant carrier type) studied are 5,5′′′‐bis(perfluorophenacyl)‐2,2′:5′,2″:5″,2′′′‐quaterthiophene ( 1 , n‐channel), 5,5′′′‐bis(perfluorohexyl carbonyl)‐2,2′:5′,2″:5″,2′′′‐quaterthiophene ( 2 , n‐channel), pentacene ( 3 , p‐channel); 5,5′′′‐bis(hexylcarbonyl)‐2,2′:5′,2″:5″,2′′′‐quaterthiophene ( 4 , ambipolar), 5,5′′′‐bis‐(phenacyl)‐2,2′: 5′,2″:5″,2′′′‐quaterthiophene ( 5 , p‐channel), 2,7‐bis((5‐perfluorophenacyl)thiophen‐2‐yl)‐9,10‐phenanthrenequinone ( 6 , n‐channel), and poly(N‐(2‐octyldodecyl)‐2,2′‐bithiophene‐3,3′‐dicarboximide) ( 7 , n‐channel). Fits of the effective field‐effect mobility (µ_eff) data assuming a discrete trap energy within a multiple trapping and release (MTR) model reveal low activation energies (E_As) for high‐mobility semiconductors 1 – 3 of 21, 22, and 30 meV, respectively. Higher E_A values of 40–70 meV are exhibited by 4 – 7 ‐derived FETs having lower mobilities (µ_eff). Analysis of these data reveals little correlation between the conduction state energy level and E_A, while there is an inverse relationship between E_A and µ_eff. The first variable‐temperature study of an ambipolar organic FET reveals that although n‐channel behavior exhibits E_A = 27 meV, the p‐channel regime exhibits significantly more trapping with E_A = 250 meV. Interestingly, calculated free carrier mobilities (µ₀) are in the range of ～0.2–0.8 cm² V^?1 s^?1 in this materials set, largely independent of µ_eff. This indicates that in the absence of charge traps, the inherent magnitude of carrier mobility is comparable for each of these materials. Finally, the effect of temperature on threshold voltage (V_T) reveals two distinct trapping regimes, with the change in trapped charge exhibiting a striking correlation with room temperature µ_eff. The observation that E_A is independent of conduction state energy, and that changes in trapped charge with temperature correlate with room temperature µ_eff, support the applicability of trap‐limited mobility models such as a MTR mechanism to this materials set.     

Polarity Effects of Polymer Gate Electrets on Non‐Volatile Organic Field‐Effect Transistor Memory

Organic non‐volatile memory (ONVM) based on pentacene field‐effect transistors (FETs) has been fabricated using various chargeable thin polymer gate dielectrics—termed electrets—onto silicon oxide insulating layers. The overall transfer curve of organic FETs is significantly shifted in both positive and negative directions and the shifts in threshold voltage (V_Th) can be systemically and reversibly controlled via relatively brief application of the appropriate external gate bias. The shifted transfer curve is stable for a relatively long time—more than 10⁵ s. However, this significant reversible shift in V_Th is evident only in OFETs with non‐polar and hydrophobic polymer electret layers. Moreover, the magnitude of the memory window in this device is inversely proportional to the hydrophilicity (determined from the water contact angle) and dielectric polarity (determined from the dielectric constant), respectively. Memory behaviors of ONVM originate from charge storage in polymer gate electret layers. Therefore, the small shifts in V_Th in ONVM with hydrophilic and polar polymers may be due to very rapid dissipation of transferred charges through the conductive channels which form from dipoles, residual moisture, or ions in the polymer electret layers. It is verified that the surface or bulk conductivities of polymer gate electret layers played a critical role in determining the non‐volatile memory properties.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

Bilayer Organic–Inorganic Gate Dielectrics for High‐Performance,Low‐Voltage,Single‐Walled Carbon Nanotube Thin‐Film Transistors,Complementary Logic Gates,and p–n Diodes on Plastic Substrates

High‐capacitance bilayer dielectrics based on atomic‐layer‐deposited HfO₂ and spin‐cast epoxy are used with networks of single‐walled carbon nanotubes (SWNTs) to enable low‐voltage, hysteresis‐free, and high‐performance thin‐film transistors (TFTs) on silicon and flexible plastic substrates. These HfO₂–epoxy dielectrics exhibit excellent properties including mechanical flexibility, large capacitance (up to ca. 330 nF cm^–2), and low leakage current (ca. 10^–8 A cm^–2); their low‐temperature (ca. 150 °C) deposition makes them compatible with a range of plastic substrates. Analysis and measurements of these dielectrics as gate insulators in SWNT TFTs illustrate several attractive characteristics for this application. Their compatibility with polymers used for charge‐transfer doping of SWNTs is also demonstrated through the fabrication of n‐channel SWNT TFTs, low‐voltage p–n diodes, and complementary logic gates.     

Printed,Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

The effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm² V^?1 s^?1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (I_on/I_off ≈ 10⁵), and a long extrapolated retention time (>10⁷ s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high I_on/I_off (≈10^{4 ± 0.85}), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.     

Orders‐of‐Magnitude Reduction of the Contact Resistance in Short‐Channel Hot Embossed Organic Thin Film Transistors by Oxidative Treatment of Au‐Electrodes

In this study we report on the optimization of the contact resistance by surface treatment in short‐channel bottom‐contact OTFTs based on pentacene as semiconductor and SiO₂ as gate dielectric. The devices have been fabricated by means of nanoimprint lithography with channel lengths in the range of 0.3 μm < L < 3.0 μm. In order to reduce the contact resistance the Au source‐ and drain‐contacts were subjected to a special UV/ozone treatment, which induced the formation of a thin AuO_x layer. It turned out, that the treatment is very effective (i) in decreasing the hole‐injection barrier between Au and pentacene and (ii) in improving the morphology of pentacene on top of the Au contacts and thus reducing the access resistance of carriers to the channel. Contact resistance values as low as 80 Ω cm were achieved for gate voltages well above the threshold. In devices with untreated contacts, the charge carrier mobility shows a power‐law dependence on the channel length, which is closely related to the contact resistance and to the grain‐size of the pentacene crystallites. Devices with UV/ozone treated contacts of very low resistance, however, exhibit a charge carrier mobility in the range of 0.3 cm² V^–1 s^–1 < μ < 0.4 cm² V^–1 s^–1 independent of the channel length.