体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

体硅CMOS FinFET结构与特性研究

建立在SOI衬底上的 FinFET结构被认为是最具全面优势的非常规MOS器件结构.本文通过合理的设计将FinFET结构迁移到普通体硅衬底上,利用平面凹槽器件的特性解决了非绝缘衬底对器件短沟道效应的影响,同时获得了一些标准集成电路工艺上的改进空间.运用标准CMOS工艺实际制作的体硅CMOS FinFET器件获得了较好的性能结果并成功地集成到CMOS反相器和环形振荡器中.结构分析与实验结果证明了体硅CMOS FinFET在未来电路中的应用前景.     

基于体硅衬底制作全耗尽FinFET器件的工艺方案

随着MOS器件缩小到纳米尺寸,为了改善器件性能,三维全耗尽FinFET器件受到广泛关注和研究.基于体硅衬底,已实现不同结构的FinFET,如双栅、三栅、环栅等结构.不同于SOI衬底FinFET,对于双栅或三栅结构,体硅衬底制作FinFET可能存在源漏穿通问题,对于环栅FinFET器件,工艺实现是一个很大的挑战.综述了目前解决源漏穿通问题的各种工艺方案,提出了全新的基于体硅衬底制作环栅FinFET的工艺方案,并展示了关键步骤的具体工艺实验结果.     

0.8 μm PDSOI CMOS器件和环振电路研究

研究了0.8μm部分耗尽绝缘体上硅(PDSOI)CMOS器件和电路,开发出成套的0.8μmPDSOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路.其中,当工作电压为5 V时,基于浮体SOI CMOS技术的0.8μm 101级环振单级延时为49.5 ps;基于H型栅体引出SOI CMOS技术的0.8μm 101级环振单级延时为158 ps.同时,对PDSOI CMOS器件的特性,如浮体效应、背栅特性、反常亚阈值斜率、击穿特性和输出电导变化等进行了讨论.     

薄膜全耗尽SOI CMOS器件和电路

对全耗尽SOI(FD SOI)CMOS器件和电路进行了研究,硅膜厚度为70nm.器件采用双多晶硅栅结构,即NMOS器件采用P+多晶硅栅,PMOS器件采用N+多晶硅栅,在轻沟道掺杂条件下,得到器件的阈值电压接近0.7V.为了减小源漏电阻以及防止在沟道边缘出现空洞(Voids),采用了注Ge硅化物工艺,源漏方块电阻约为5.2Ω/□.经过工艺流片,获得了性能良好的器件和电路.其中当工作电压为5V时,0.8μm 101级环振单级延迟为45ps.     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

两微米外延N阱CMOS艺的研究

本文描述2μm外延N阱CMOS工艺的研究,在工艺模拟和实验的基础上制定了合理的、可行的工艺流程.在工艺中成功地应用了全离子注入和红外瞬态退火技术.实验结果表明,2μm CMOS 器件具有优良的特性,适合超大规模集成电路的要求.5伏工作电压,21级2μmCMOS反相器环振链的级延时是0.48ns,每级的延时功耗乘积是0.49pJ.P~-/P~+外延层结合N阱伪集电极保护环,可在CMOS电路中最易产生Latch-up的I/O电路部分保证不发生Latch-up.本工艺可以应用于超大规模集成电路的制作.     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

FinFET器件总剂量效应研究进展

全面综述鳍式场效应晶体管(FinFET)的总剂量效应,包括辐照期间外加偏置、器件的工艺参数、提高器件驱动能力的特殊工艺、源/漏掺杂类型以及不同栅介质材料和新沟道材料与FinFET总剂量效应的关系。对于小尺寸器件,绝缘体上硅(SOI)FinFET比体硅FinFET具有更强的抗总剂量能力,更适合于高性能抗辐照的集成电路设计。此外,一些新的栅介质材料和一些新的沟道材料的引入,如HfO₂和Ge,可以进一步提高FinFET器件的抗总剂量能力。     

标准CMOS工艺低压栅控硅发光器件设计与制备

本文采用0.18μm标准CMOS工艺设计并制备了一种MOS结构的低压栅控硅基发光器件.该光源器件内部采用n+-p+-p+-n+-p+-p+-n+的叉指结构,在相邻两个p+有源区之间覆盖多晶硅栅作为第三端控制电极,用于在源/漏区边缘形成场诱导结,降低p+/n-well结的反向击穿电压,提高器件发光功率.测试结果表明,该光源器件可以发射420nm～780nm的黄色可见光,在3V的正向栅压下,p+/n-well发光二极管的反向击穿电压下降到3V以下,光输出功率提高至2倍以上.本文设计的光源器件工作电压较低,并且与CMOS工艺完全兼容,可以与其他CMOS电路共用电源并且实现单片集成,在硅基光电子集成领域具有一定的应用价值.     

Co-integration of GaAs MESFET and Si CMOS circuits

Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2-μm gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1-μm gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated     

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

A series FinFET based non-volatile logic gates with multiple logic functions defined by embedded non-volatile states are proposed for the first time and demonstrated in advanced CMOS technology platform. The device channels in the proposed CMOS logic gate is controlled by a metal floating gate coupled by slot contacts uniquely available in the FinFET process employed in this study. The new logic gate with non-volatile states only enable reconfiguration ability in a Boolean computing unit at a gate level aimed for adaptive and specialized systems in the AI era. Furthermore, the extended applications in tunable ring oscillators for multi-functional IOT modules are successfully demonstrated in this study.     

A high-performance CMOS/SOS device with a gradually doped source—Drain extension structure

A gradually doped source-drain extension (GDDE) CMOS/SOS structure with n+ poly gate has been used to fabricate a high-performance CMOS/SOS inverter ring oscillator and 1%8 static binary counter. The 0.8-µm gate ring oscillator shows 80-ps stage delay atV_{DD} = 5V, and it achieves 0.1 pJ of speed-power product with 95-ps stage delay. The plasma-etched epi island minimizes the edge leakage current, as shown in subthreshold characteristics.     

Area efficient layout design of CMOS circuit for high-density ICs

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher I_on to I_off ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.     

Si-gate CMOS devices on a Si/CaF2/Si structure

Si-gate CMOS inverter chains and 1/8 dynamic frequency dividers have been fabricated on a Si/CaF2/Si structure. A high-quality heteroepitaxial Si/CaF2/Si structure was formed by successive molecular-beam epitaxy of CaF2and Si. Transistors have been fabricated with an improved CMOS process that prevents crystal degradation during the fabrication process as much as possible. The maximum effective mobilities are about 570 and 240 cm²/V . s for n-channel and p-channel transistors, respectively. The inverter chain with an effective channel length of 2.0 µm has a delay time per gate of 360 ps. A maximum operating frequency of 300 MHz is obtained in the divider with an effective channel length of 2.5µm at a supply voltage of 5 V. These results indicate that the Si/CaF2/Si structure has potential for the fabrication of high-speed silicon-on-insulator devices.     

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried $hbox{Si}_{1 - y}hbox{C}_{y}$ Substrate for Multifunctioning Flash Memory and 1T-DRAM

A band-offset-based unified-RAM (URAM) cell fabricated on a Si/$ hbox{Si}_{1 - y}hbox{C}_{y}$ substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered $hbox{Si}_{1 - y}hbox{C}_{y}$ substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.      

High-speed BiCMOS technology with a buried twin well structure

A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (fT= 4 GHz) and small size (500 µm²) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.     

Fin-height controlled TiN-gate FinFET CMOS based on experimental mobility

This paper presents the fin-height controlled TiN-gate FinFET CMOS technology based on the experimental carrier mobility data. The good current matching by tuning the N-channel fin-height and the excellent transfer performance in the fabricated TiN-gate CMOS inverter are demonstrated. The developed technologies are attractive to materialize the high-performance FinFET CMOS circuits.