Threshold logic circuit design of parallel adders using resonanttunneling devices

Resonant tunneling devices and circuit architectures based on monostable-bistable transition logic elements (MOBILEs) are promising candidates for future nanoscale integration. In this paper, the design of clocked MOBILE-type threshold logic gates and their application to arithmetic circuit components is investigated. The gates are composed of monolithically integrated resonant tunneling diodes and heterostructure field-effect transistors. Experimental results are presented for a programmable NAND/NOR gate. Design related aspects such as the impact of lateral device scaling on the circuit performance and a bit-level pipelined operation using a four phase clocking scheme are discussed. The increased computational functionality of threshold logic gates is exploited in two full adder designs having a minimal logic depth of two circuit stages. Due to the self-latching behavior the adder designs are ideally suited for an application in a bit-level pipelined ripple carry adder. To improve the speed a novel pipelined carry lookahead addition scheme for this logic family is proposed     

Timing-driven logic restructuring for nano-hybrid circuits

As the feature size of the integrated circuits (ICs) scales down, the future of nano-hybrid circuit looks bright in extending Moore's Law. However, mapping a circuit to a nano-fabric structure is vexing due to connectivity constraints. A mainstream methodology is that a circuit is transformed into a nano-fabric preferred structure by buffer insertion to high fan-out gates. However, it may result in timing degradation. Logic replication is a traditional way to split high fan-out gates in logic synthesis but may not be suitable for high fan-out gates with high fan-ins. In this article, a timing-driven logic restructuring framework at the gate level is proposed. The proposed framework identifies the high fan-out gates from a given gate netlist according to the fan-out threshold, following by the restructuring of high fan-out gates through the application of logic replication and buffer insertion. To improve circuit timing from a global perspective, latent critical edges are identified to avoid entrapping critical paths during the restructuring. Experimental results on ISCAS benchmarks indicate that 8.51% timing improvement and 6.13% CPU time reduction can be obtained traded with 4.16% area increase on an average.     

High-speed bipolar logic circuits with low power consumption for LSI-a comparison

Various high-speed bipolar logic circuits (CML, FECL, NTL, TTL, STL) are investigated and compared which exhibit gate delays far below 1 ns, even at a very low power dissipation per gate (e.g. 0.1 mW). Therefore, these circuits are best suited for LSI. It is shown that, by tailoring the circuit components (transistors, Schottky diodes) to the power dissipation P, the expected increase of the gate delay t/SUB D/ according to t/SUB D/~1/P can be shifted to surprisingly low values of P. Further, the simulations show that the Schottky clamp technique has considerable advantages concerning the switching speed at very low power dissipations, compared with the current-mode logic known to be fast. The results are explained by simple calculations.     

Efficient reversible NOR gates and their mapping in optical computing domain

Reversible logic is a computing paradigm in which there is a one to one mapping between the input and the output vectors. Reversible logic gates are implemented in an optical domain as it provides high speed and low energy computations. In the existing literature there are two types of optical mapping of reversible logic gates: (i) based on a semiconductor optical amplifier (SOA) using a Mach–Zehnder interferometer (MZI) switch; (ii) based on linear optical quantum computation (LOQC) using linear optical quantum logic gates. In reversible computing, the NAND logic based reversible gates and design methodologies based on them are widely popular. The NOR logic based reversible gates and design methodologies based on them are still unexplored. In this work, we propose two NOR logic based n-input and n-output reversible gates one of which can be efficiently mapped in optical computing using the Mach–Zehnder interferometer (MZI) while the other one can be mapped efficiently in optical computing using the linear optical quantum gates. The proposed reversible NOR gates work as a corresponding NOR counterpart of NAND logic based Toffoli gates. The proposed optical reversible NOR logic gates can implement the reversible boolean logic functions with a reduced number of linear optical quantum logic gates or reduced optical cost and propagation delay compared to their implementation using existing optical reversible NAND gates. It is illustrated that an optical reversible gate library having both optical Toffoli gate and the proposed optical reversible NOR gate is superior compared to the library containing only the optical Toffoli gate: (i) in terms of number of linear optical quantum gates when implemented using linear optical quantum computing (LOQC), (ii) in terms of optical cost and delay when implemented using the Mach–Zehnder interferometer.     

基于DNA链置换的三级联组合分子逻辑电路设计

DNA计算研究内容繁多复杂,DNA复杂逻辑电路的搭建属于DNA计算的一个重要研究分支,其中逻辑门的构建属于DNA复杂逻辑电路搭建的基础研究,设计出更为简单的逻辑门可以为研究者搭建复杂电路提供参考,节省基础研究的宝贵时间。针对上述问题,该文利用使能控制端思想,采用DNA链置换技术,设计了与或、与非或非和异或同或3种DNA组合逻辑门。结果显示,设计的3种组合逻辑门可实现6种逻辑运算功能,并利用所构建的组合逻辑门成功构造了多级联组合分子逻辑电路,为DNA计算提供了更多的解决方案,促进了DNA计算机的发展。     

Parallel Adder Design with Reduced Circuit Complexity Using Resonant Tunneling Transistors and Threshold Logic

Quantum-effect devices utilizing resonant tunneling are promising candidates for future nano-scale integration. Originating from the technological progress of semiconductor technology, circuit architectures with reduced complexity are investigated by exploiting the negative-differential resistance of resonant tunneling devices. In this paper a resonant tunneling device threshold logic family based on the Monostable-Bistable Transition Logic Element (MOBILE) is proposed and applied to different parallel adder designs, such as ripple carry and binary carry lookahead adders. The basic device is a resonant tunneling transistor (RTT) composed of a resonant tunneling diode monolithically integrated on the drain contact layer of a heterostructure field effect transistor. On the circuit level the key components are a programmable NAND/NOR logic gate, threshold logic gates, and parallel counters. The special properties of MOBILE logic gates are considered by a bit-level pipelined circuit style. Experimental results are presented for the NAND/NOR logic gate.     

All-optical 40 Gbit/s XOR gate with dual ultrafast nonlinear interferometer

A novel XOR logic gate using dual cascaded ultrafast nonlinear interferometer elements based on semiconductor optical amplifiers is proposed and demonstrated at 40 Gbit/s. The gate is switched at the line rate rather than twice line rate, as in previously reported differential XOR gates.     

A 30-ps Josephson current injection logic (CIL)

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.     

Characterization of heterostructure complementary MISFET circuits employing the new gate current model

A complementary logic circuit employing heterostructure MISFET's is shown to have a larger logic swing and noise margin than an E/D MESFET logic circuit. The noise margin is calculated using a new gate current model that is derived by taking into account the small surface potential dependence on the gate voltage at the heterointerface. The circuit simulation indicates that, for multi-input logic gates, a NAND gate configuration is superior to a NOR gate configuration from the viewpoints of noise margin and switching speed. The normalized high- and low-level noise margins are comparatively balanced (34 and 49 percent) for a three-input NAND gate. For a fan-in/fan-out of 3/3 and a 100-fF wiring capacitance condition, a 54-ps delay time and 57-μW power dissipation/gate at a 100-MHz clock frequency are possible for a NAND gate with 0.5-μm gate-length MISFET's at 77 K.     

Compatible cell connections for multifamily dynamic logic gates

Dynamic logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections is then identified and later applied to discover which are the feasible connections between cell circuit types identified.     

Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices

The circuit concept of programmable logic gates based on the controlled quenching of series-connected negative differential resistance (NDR) devices is introduced, along with the detailed logic synthesis and circuit modeling. At the rising edge of a clocked supply voltage, the NDR devices are quenched in the ascending order of peak currents that can be reordered by the control gates and input gates biases, thus, providing programmable logic functions. The simulated results agree well with the experimental demonstration of the programmable logic gate fabricated by a monolithic integrated resonant tunneling diode/high electron mobility transistor technology.     

GaAs trickle transistor dynamic logic

A GaAs dynamic logic gate is proposed which uses a trickle transistor to compensate for leakage from the precharged node. This trickle transistor dynamic logic (TTDL) circuit is configured as a domino logic gate and a differential cascode voltage switch logic (CVSL) gate. Delay chains were implemented in a 1-μm GaAs enhancement/depletion (E/D) process where the depletion-mode FETs (DFETs) and the enhancement-mode FETs (EFETs) have threshold voltages of -0.6 and 0.15 V, respectively, in order to obtain an experimental characterization of these gates. In addition, the TTDL gates were used to implement a 4-b carry-lookahead adder. The adder has a critical delay of 0.8 ns and a power dissipation of 130 mW     

Simultaneous All-Optical and and nor Gates for NRZ Differential Phase-Shift-Keying Signals

A scheme for realizing all-optical logic AND and NOR gates simultaneously for nonreturn-to-zero differential phase-shift-keying signals is proposed and demonstrated based on a delayed interferometer and two semiconductor optical amplifiers. Experimental demonstration at 20 Gb/s verifies the logic integrity of this scheme. The final results are derived in the ON-OFF keying format with clear open eyes and extinction ratios over 10 dB. The proposed scheme can be expanded to realize arbitrary logic gate.     

光电子混合模糊逻辑

本文提出了一种由光电子混合回路构成的简单光学模糊逻辑门设计。演示了补、最大、最小和限界差(相对补)四种最基本的逻辑操作。给出了一个多功能可编程的光电子混合模糊逻辑门,可实现模糊逻辑中七种基本逻辑运算。     

All-optical logic NXOR based on semiconductor optical amplifiers with the effect of amplified spontaneous emission

The performance of all-optical logic NXOR gate based on semiconductor optical amplifiers Mach-Zehnder interferometer(SOAs-MZI)is simulated.The effects of amplified spontaneous emission(ASE)and the input pulse energy on the system’s quality factor are studied.For the parameters used,the all-optical logic gates using SOAs are capable of operating at speed of 80Gbit/s.     

Low power optical gate HBT driver array for 2.5 Gbit/s ATMswitching

A four element driver array for optical gates in a 2.5 Gbit/s optical ATM switch is presented. The circuit uses a GaAs-GaAlAs heterojunction bipolar transistor (HBT) technology. It enables a switching time of <300 ps and current up to 150 mA with <400 mW per gate power consumption     

STS-768 multiplexer with full-rate output data retimer in InP HBT

A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance.     

On the design robustness of threshold logic gates using multi-inputfloating gate MOS transistors

In this paper, the design robustness of logic circuits implemented as threshold logic gates with multi-input floating gate transistors is analyzed. The parameter variations of the basic components, namely the coupling capacitances of the floating gate MOSFETs and the sensing circuits for obtaining full logic levels, are investigated separately using appropriate array test structures. It is found that the dominant mismatch originates from the input offset voltage variations of the sensing circuits. Methods are presented for estimating the yield of a given logic circuit from the measured parameter distributions. The estimations are verified with measured data of a multiplier cell and of the encoding logic in a parallel fingerprint sensor architecture. Considerations are given for robust design of circuits based on threshold logic gates that use floating gate transistors     

10 K-gate GaAs JFET sea of gates

The first GaAs 10 K-gate sea of gates has been successfully fabricated using junction FETs (JFETs) with a gate length of 0.5 μm. A basic cell is designed to comprise both a direct coupled FET logic (DCFL) four-NOR circuit and a source coupled FET logic (SCFL) inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si emitter-coupled-logic (ECL), CMOS, and transistor-transistor-logic (TTL) levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is 3.9 and 4.4 GHz for DCFL and SCFL, respectively     

Dynamic internal testing of CMOS circuits using hot luminescence

Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the dynamics of all the gates of the circuit are simultaneously measured. This noninvasive technique can be extended to smaller device size, as well as probing from the backside of the wafer. The optical emission may provide an alternative to electron beam testing for measuring the dynamics of high-speed CMOS circuits