Design and analysis of kinematically redundant parallel manipulators with configurable platforms

Redundancy can, in general, improve the ability and performance of parallel manipulators by implementing the redundant degrees of freedom to optimize a secondary objective function. Almost all published researches in the area of parallel manipulators redundancy were focused on the design and analysis of redundant parallel manipulators with rigid (nonconfigurable) platforms and on grasping hands to be attached to the platforms. Conventional grippers usually are not appropriate to grasp irregular or large objects. Very few studies focused on the idea of using a configurable platform as a grasping device. This paper highlights the idea of using configurable platforms in both planar and spatial redundant parallel manipulators, and generalizes their analysis. The configurable platform is actually a closed kinematic chain of mobility equal to the degree of redundancy of the manipulator. The additional redundant degrees of freedom are used in reconfiguring the shape of the platform itself. Several designs of kinematically redundant planar and spatial parallel manipulators with configurable platform are presented. Such designs can be used as a grasping device especially for irregular or large objects or even as a micro-positioning device after grasping the object. Screw algebra is used to develop a general framework that can be adapted to analyze the kinematics of any general-geometry planar or spatial kinematically redundant parallel manipulator with configurable platform.     

A configurable, virtual microprocessor system for instructional usein real-time, real-world studies

A system that allows students to simulate an validate a process plant of their own design, associate I/O channels to the individual components of it, and write a control or sequencer program to control the plant operation using any given assembler is described. Instructors can add a control section to the system that will produce random faults, power failures, and input/output errors in a simulation. With this capability, instructors can test a student's design for completeness, error handling, and fail-safe operation. Some self-correcting faults simulate a repair; the control program restarts as and when appropriate, while other conditions must close the plant down. In the graphics mode of operation the plant design appears as a cartoon with fluid levels altering, pumps switching on and off, and so on, according to the control effected by the student program. The system also displays a trace of the execution and I/O status of the program under execution. If no process design is included, the system can be used to run simple assembler programs on a stand-alone basis. The system was written in response to a need for a teaching tool usable in graduate-level real-time, real-world computing courses     

Implementation of a RISC microprocessor for programmable logic controllers

A special purpose RISC (reduced instruction set computer) microprocessor for programmable logic controllers (PLC), named PLCRISC, is proposed. To develop an optimal PLCRISC, we analysed existing PLC programs currently used in factories, with special attention to the instruction execution characteristics and features required for a high performance PLC processor. Based on this analysis, an optimal RISC-style instruction set and an architecture suitable for the required features are suggested. In particular, the instruction format, the instruction pipeline, and the detailed internal architecture are the significant characteristics of the proposed PLCRISC. The performance enhancement achieved with a PLCRISC is seen from a straightforward evaluation. ASIC implementation with VHDL is also discussed. The PLCRISC is under fabrication in a 0.8 μm CMOS technology.     

A 5–10 GHz SiGe BiCMOS FPGA with new configurable logic block

This paper presents a new multiplexer based FPGA, which can operate at a clock frequency of 5–10 GHz. Redundant switches on the original signal paths are removed improving the performance. The configurable logic blocks (CLBs) power is greatly reduced by using a revised multiplexer structure and turning off unused cells dynamically. More routing capabilities are provided with more inputs/outputs in each direction than similar designs. A chip consisting of four FPGA ring oscillators was fabricated. The Spice simulation results and chip measurements are presented.     

Reconceptualizing platforms in information systems research through the lens of service-dominant logic

Platforms have gained significant attention in the field of information systems (IS) research. However, the concept of platforms remains fluid and complex due to the diverse phenomena associated with it. Research to date tends to cluster around two predominant perspectives: the economic network perspective and the architectural design perspective. To reconcile the divergent perspectives of platforms and establish a more cohesive foundation for IS theorizing, we undertake an interpretive literature review through the lens of service-dominant (S-D) logic. Drawing on an extensive analysis of the literature, we develop an S-D Platform Framework that provides a deep understanding of the multifaceted nature of platforms as a vital IS capability for value co-creation. This framework sheds light on the fundamental facets of relationality, ambidexterity, and cooperativity, which explain the deep structure of platforms in the realm of IS research. Building on our proposed framework, we put forth an agenda that aims to guide future studies towards a more theoretically compelling trajectory.     

Flexible and configurable verification policies with Omnibus

The three main assertion-based verification approaches are: run-time assertion checking (RAC), extended static checking (ESC) and full formal verification (FFV). Each approach offers a different balance between rigour and ease of use, making them appropriate in different situations. Our goal is to explore the use of these approaches together in a flexible way, enabling an application to be broken down into parts with different reliability requirements and different verification approaches used in each part. We explain the benefits of using the approaches together, present a set of guidelines to avoid potential conflicts and give an overview of how the Omnibus IDE provides support for the full range of assertion-based verification approaches within a single tool.     

Piezoelectric microphone with on-chip CMOS circuits

An IC-processed piezoelectric microphone with on-chip, large-scale integrated (LSI) CMOS circuits has been designed, fabricated, and tested in a joint, interactive process between a commercial CMOS foundry and a university micromachining facility. The 2500×2500×3.5 μm ³ microphone has a piezoelectric ZnO layer on a supporting low-pressure chemical-vapor-deposited (LPCVD), silicon-rich, silicon nitride layer. The optimum residual-stress-compensation scheme for maximizing microphone sensitivity produces a slightly buckled microphone diaphragm. A model for the sensitivity dependence of device operation to residual stress is confirmed by applying external strain. The packaged microphone has a resonant frequency of 18 kHz, a quality factor Q≈40, and an unamplified sensitivity of 0.92 mV/Pa. Differential amplifiers provide 49 dB gain with 13 μV A-weighted noise at the input     

基于Verilog HDL实现RISC微处理器

介绍基于精简指令计算机技术的8位微处理器的设计与实现,主要包括指令集取指、分析、执行、回写单元的设计;以及取指、执行、回写三级流水线技术的实现。微处理器包含8个基本部件：时钟发生器、指令寄存器、累加器、算术逻辑运算单元、数据控制器、状态控制器、程序计数器、地址译码器。设计使用可综合的Verilog HDL语言描述,采用Xilinx公司最新的集成开发工具软件ISE 6．2及该公司的XC9572 Flash工艺CPLD器件和Modelsim验证实现。     

A low-complexity microprocessor design with speculative pre-execution

Current superscalar architectures strongly depend on an instruction issue queue to achieve multiple instruction issue and out-of-order execution. However, the issue queue requires a centralized structure and mainly causes globally broadcasting operations to wakeup and select the instructions. Therefore, a large issue queue ultimately results in a low clock rate along with a high circuit complexity. In other words, the increasing demands for a larger issue queue correspondingly impose a significant burden on achieving a higher clock speed.This paper discusses our Speculative Pre-Execution Assisted by compileR (SPEAR), a low-complexity issue queue design. SPEAR is designed to manage the small window superscalar architecture more efficiently without increasing the window size. To this end, we have first recognized that the long memory latency is one of the factors that demand a large window, and we aim at achieving early execution of the miss-causing load instructions using another hierarchy of an issue queue. We pre-execute those miss-causing instructions speculatively as an additional prefetching thread. Simulation results show that the SPEAR design achieves performance comparable to or even better than what would be obtained in superscalar architectures with a large issue queue. However, SPEAR is designed with smaller issue queues which consequently can be implemented with low hardware complexity and high clock speed.     

可存盲区的井下无线传感器网络节点部署研究

在分析现有无线传感器网络节点部署方案和覆盖模型的基础上,针对完全覆盖存在难度大、成本高、节点存在冗余等缺点,提出了一种可存盲区的井下无线传感器网络覆盖模型和节点部署方案,并给出了该方案在井下的具体应用。可存盲区的井下无线传感器网络节点部署方案可根据监测对象的具体情况调节盲区度,从而实现盲区大小的设置。分析结果表明,对于相同的节点数量,该方案比完全覆盖时的覆盖面积大;对于同等面积的监测区域,该方案比完全覆盖时所需的传感器节点数量少,不仅节约了系统成本,还在一定程度上改善了节点冗余度问题。     

Energy management strategies for parallel hybrid vehicles using fuzzy logic

This paper presents a fuzzy-logic-based energy management and power control strategy for parallel hybrid vehicles (PHV). The main objective is to optimize the fuel economy of the PHV, by optimizing the operational efficiency of all its components. The controller optimizes the power output of the electric motor/generator and the internal combustion engine by using vehicle speed, driver commands from accelerator and braking pedals, state of charge (SOC) of the battery, and the electric motor/generator speed. Separate controllers optimize braking and gear shifting. Simulation results show potential fuel economy improvement relative to other strategies that only maximize the efficiency of the combustion engine.     

The density advantage of configurable computing

More and more, field-programmable gate arrays (FPGAs) are accelerating computing applications. The absolute performance achieved by these configurable machines has been impressive-often one to two orders of magnitude greater than processor-based alternatives. Configurable computing is one of the fastest, most economical ways to solve problems such as RSA (Rivest-Shamir-Adelman) decryption, DNA sequence matching, signal processing, emulation, and cryptographic attacks. But questions remain as to why FPGAs have been so much more successful than their microprocessor and DSP counterparts. Do FPGA architectures have inherent advantages? Or are these examples just flukes of technology and market pricing? Will advantages increase, decrease, or remain the same as technology advances? Is there some generalization that accounts for the advantages in these cases? The author attempts to answer these questions and to see how configurable computing fits into the arsenal of structures used to build general, programmable computing platforms     

Bidirectional differential on-chip wave-pipelined serial interconnect with surfing

In the literature, surfing technique has been proposed for differential on-chip wave-pipelined serial interconnects with uniform repeaters (UR) and non-uniform repeaters to increase the data transfer rate for unidirectional schemes. In this paper, a novel bidirectional data transfer through the differential wave-pipelined serial interconnects with surfing for UR is proposed. A new circuit called ‘Bidirectional surfing inverter pair’ is proposed for differential wave-pipelined serial interconnects. The method of logical effort is used for the design of surfing circuits. To evaluate the efficiency of these techniques, 40 mm metal 4 interconnects using the proposed surfing techniques are implemented along with transmitter, receiver and delay locked loop in UMC 180 nm technology and their performances are studied through post layout simulations. The proposed bidirectional differential surfing scheme has a maximum data transfer rate of 2 Gb/s and has allowable jitter of 52 ps on both directions through the same interconnects.     

Highly reliable testing of ULSI memories with on-chip voltage-downconverters

Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V_CC to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal V_CC levels during the water sort test (WT) and the final shipping test (FT)     

Qualitative trust model with a configurable method to aggregate ordinal data

Trust models are mechanisms that allow agents to build trust without relying on a trusted central authority. Our goal was to develop a trust model that would operate with values that humans easily understand and manipulate: qualitative and ordinal values. The result is a trust model that computes trust from experiences created in interactions and from opinions obtained from third-party agents. The trust model, termed qualitative trust model (QTM), uses qualitative and ordinal values for assessing experiences, expressing opinions and estimating trust. We treat such values appropriately; we never convert them to numbers, but merely use their relative order. To aggregate a collection of such values, we propose an aggregation method that is based on comparing distributions and show some of its properties; the method can be used in other domains and can be seen as an alternative to median and similar methods. To cope with lying agents, QTM estimates trustworthiness in opinion providers with a modified version of the weighted majority algorithm, and additionally combines trustworthiness with social links between agents; such links are obtained implicitly by observing how agents provide opinions about each other. Finally, we compare QTM against a set of well-known trust models and demonstrate that it consistently performs well and on par with other quantitative models, and in many cases even outperforms them, particularly when the number of direct experiences is low.     

Analog implementation of a Kohonen map with on-chip learning.

Kohonen maps are self-organizing neural networks that classify and quantify n-dimensional data into a one- or two-dimensional array of neurons. Most applications of Kohonen maps use simulations on conventional computers, eventually coupled to hardware accelerators or dedicated neural computers. The small number of different operations involved in the combined learning and classification process, however, makes the Kohonen model particularly suited to a dedicated VLSI implementation, taking full advantage of the parallelism and speed that can be obtained on the chip. A fully analog implementation of a one-dimensional Kohonen map, with on-chip learning and refreshment of on-chip analog synaptic weights, is proposed. The small number of transistors in each cell allows a high degree of parallelism in the operations, which greatly improves the computation speed compared to other implementations. The storage of analog synaptic weights, based on the principle of current copiers, is emphasized. It is shown that this technique can be used successfully for the realization of VLSI Kohonen maps.