晶体管功率老化台

晶体三极管是电子设备的主要元件,其质量的好坏直接影响电子设备整机的稳定性和可靠性。因此,在电子设备的整机生产之前必须对晶体三极管进行筛选,其中对晶体三极管进行功率老化是筛选晶体三极管的一项重要的工艺。要对大批量的晶体三极管进行功率老化筛选,采用一般的人工老化设备是远远不能     

HM6232/6236厚膜组件的修复方法

HM6232/6286是NP8C系列机芯的场输出厚膜组件,由组件的电原理圈可知(见图)其电路由三个晶体三极管、11个电阻及一个热敏元件所组成。该组件的晶体三极管、电阻及连线都直接焊接和印制在陶瓷基板上。而场输出级功耗较大、热量较高,相对来说组件发生故障的可能性略高。而故障一般都以印刷电阻或镀银连线断裂较为常见。也有的     

神通广大的晶体三极管

晶体三极管简称晶体管或三极管,是一种具有两个PN结的半导体器件。晶体三极管的最大特点是具有电流放大及控制作用,它是在电子线路中被广泛使用的重要电流控制型器件。利用晶体三极管的特性,可以组成放大、振荡、开关等各种功能的电子电路。     

计算串联稳压电路调整管的最大功耗的另一种方法

串联稳压电路主要工作在线性状态,因此调整管的功耗大。很多情况下调整管的损坏系因其功耗过大发热所致,所以计算调整管的最大功耗是选择调整管的关键,但一些教材中对调整管功耗的计算方法不够严密。本文利用最大功率传递定理,对调整管的最大功耗进行了分析计算。     

晶体三极管奇妙的电流放大作用

晶体三极管是电子电路中最基本而常用的放大和开关器件,不论在分立元件电路,还是集成电路中处处都有它的身影,因此弄清晶体三极管的工作原理,掌握其基本的工作电路是十分必要的,初学者一定要在这方面狠下功夫,建立清楚的概念。一、晶体三极管的结构晶体三极管是由P型与N型半导体构成的,有两种基本     

电子元器件实用知识讲座(7)

<正> 第七讲 晶体三极管(上) 晶体三极管又叫半导体三极管,通常简称为晶体管或三极管。三极管大都是具有3个外部电极(引出脚)的半导体器件。少数三极管有4根引脚,但其中1根引脚为接地等用,与“三极”的功能无关。三极管的基本特性是对电信号进行放大和开关,其在电子电路中的应用十分广泛,是电子设备中的核心器件之一。在收音机、电视机、扩音机、录像机及计算机等许多电子电器整机中均可见到这种器件。     

自制石英晶体测试器

本文介绍的石英晶体测试器,是利用发光二极管来提示检测结果,既快又比较准确。该石英晶体测试器电路如附图所示。把待测石英晶体BX插入插座P1、P2,按下按钮SB,若BX是好的,则由于三极管VT1、电容C1、C2等元件构成的振荡器工作,振荡信号由VT1发射极输出,再由C3直接耦合到VD2进行检波,变成直流信号电压并送至VT2基极,使三极管VT2获得正向偏置电压信号而导通,发光二极管LED发光,确认这只被测石英晶体是好的。若LED不亮,则表示被测石英晶体是坏的。     

单片机系统中减少功耗的几个实用技巧

本文介绍了单片机系统中通过改进软件设计减少LED功耗及三极管功耗的几个实用技巧。     

第八讲 开关稳压电源中的元器件

一、功率开关元件脉宽调制(PWM)型开关稳压电源中的功率开关元件,主要是功率晶体三极管.但随着开关稳压电源趋向小型化、高频化发展,V-MOS功率场效应晶体管也得到应用.在某些调频型开关稳压电源中,还用到高频可控硅. (一)功率晶体三极管脉宽调制型开关稳压电源中的功率晶体三极管,因工作在高压开关状态,其性能的优劣会直接影响到开关稳压电源的性能和可靠性。在选用功率三极管时,必须从它的电气性能来考     

模拟电路中三极管和运放的软故障诊断

基于文献[1]中的斜率故障模型,提出了一种诊断模拟电路中晶体三极管和集成运算放大器软故障的字典法.在含有三极管和运放的电路中,通过对三极管和运放进行等效模型替代,对替代之后的等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现原电路中三极管和运放的软故障诊断.给出了三极管和运放的等效模型分析和诊断步骤,并用仿真实例证明了诊断方法的有效性.     

The effects of BJT self-heating on circuit behavior

This study demonstrates the circuit and device conditions under which self-heating can significantly affect bipolar junction transistor (BJT) circuit behavior. Simple quantitative measures are supplied that allow estimation of thermally induced errors in BJT small-signal parameters, based on knowledge of the transistor geometry and its Early voltage. It is shown that errors in output admittance and reverse transadmittance can be significant without much power dissipation, especially when the base and emitter driving impedances are small. Other small-signal parameters are less affected unless the power dissipation becomes significant. Thermal effects in large-signal DC analysis can be significant in precision analog circuits that depend on close transistor matching; such circuits can also exhibit long settling-time tails due to long thermal time constants. ECL (emitter-coupled logic) delay is shown to be insensitive to self-heating. These effects are demonstrated through simulations of a variety of circuits using versions of SPICE modified to include physics-based models for thermal impedance     

有射极电阻的基本电路中双极型晶体三极管工作状态的一种判断方法

本文给出含有射极电阻的基本电路中双极型晶体三极管(BJT)工作状态的一种判断方法。对于有射极电阻的基本电路,如果只知道电路中电阻的阻值、BJT的电流放大倍数β和直流电源的电压值,可以先假设其中的BJT处于放大状态,求出BJT在放大状态下的集电极电流IC或基极电流IB,然后与临界饱和状态下的集电极电流ICS或基极电流IBS比较,如果IC相似文献   

Van der Waals Bipolar Junction Transistor Using Vertically Stacked Two‐Dimensional Atomic Crystals

The majority of microelectronic devices rely on a p‐n junction. The process of making such a junction is complicated, and it is difficult to make layers that form a junction with an atomic thickness. In this study, bipolar junctions are made by using 2D atomic crystalline layers and even a single layer in which 2D layers adhere together to form a heterostructure via van der Waals forces. A vertical 2D bipolar junction transistor (V2D‐BJT) is studied for the first time. It uses an MoS₂/WSe₂/MoS₂ heterostructure and has an n‐p‐n configuration that exhibits a maximum common‐base current gain of ≈0.97 and a stable common‐emitter current gain (β) of 12 with a nanowatt power consumption. In the first attempt at gas sensing, it shows outstanding performance, exhibiting a very fast response and recovery time (9 and 35 s, respectively) with a power dissipation of only 2 nW. This study demonstrates the potential application of the V2D‐BJT in nanowatt power amplifiers as well as fast‐response and low‐power gas sensors.     

Closed-form breakdown voltage model for PD SOI NMOS devices considering impact ionization of both parasitic BJT and surface MOS channel simultaneously

This paper reports a compact breakdown voltage model for partially depleted (PD) silicon-on-insulator (SOI) n-metal-oxide-semiconductor (NMOS) devices considering BJT/MOS impact ionization. Via the improved current conduction model considering BJT/MOS impact ionization this compact model provides an accurate prediction of the breakdown behavior of the PD SOI NMOS devices as verified by the experimental data and the MEDICI results. Based on the analytical model, when the gate voltage is lowered, the breakdown voltage decreases due to a stronger function of the parasitic BJT. In the subthreshold region, the breakdown voltage increases at a decreased gate voltage due to a weaker function of the parasitic BJT.     

芯片设计中的功耗估计与优化技术

在芯片设计中,低功耗一直是一个重要的目标,受到封装、供电、散热的约束,并且最大功耗限制越来越严格。在本文中,首先讨论了芯片中的功耗来源。接着,阐述了在设计过程初期可以采用的几项可以降低功耗的技巧。本文提出的方法用于架构设计和前段设计的初期,如功耗估计、低功耗架构优化和时钟门控等。     

BJMOSFET温度特性分析及计算机模拟

对兼有双极型和场效应型两种器件特点的双极MOS场效应晶体管(BJMOSFET)的电流和阈值电压的温度特性进行了详细分析．推导出它们随温度变化率的解析表达式。建立BJMOSFET的直流小信号模拟分析等效电路和频率特性模拟分析等效电路,采用通用电路仿真软件PSpice9,对BJMOSFET的输出特性、瞬态特性和幅频特性随温度的变化进行了计算机模拟,得到了随温度变化的特性曲线,并且理论分析与计算机模拟取得了一致的结果。相对传统MOSFET,证明了BJMOSFET具有较好的温度特性。     

Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies

As technology scales down into the ultra deep-submicron (UDSM) region, the static power dissipations grow exponentially and become an increasingly dominant component of the total power dissipation in CMOS circuits. With increase in gate leakage current resulting from thinner gate oxides in UDSM and the problems associated with short channel effects, leakage power dissipation is becoming a huge factor challenging a continuous success of CMOS technology in the semiconductor industry. With strict limitations of maximum allowable power (the power being limited more by system level cooling and test constraints than packaging) of 2.8 W (in 2005) to 3 W (in 2020) for battery (low cost/handheld) operated devices as projected by the International Technology Roadmap for Semiconductors (ITRS) 2005, innovations in leakage control and management are urgently needed. This paper presents an overview of the sources of the power dissipation mechanisms in the UDSM technologies, and the device and circuit techniques to control them.     

平面结构4H-SiC BJT击穿特性及终端技术研究

4H-SiC双极晶体管（BJT）主要应用于大功率器件,器件的阻断特性是最重要的性质之一,因此提高器件的耐高压能力非常重要。国内外的高校和研究机构在SiC器件击穿特性的研究方面进行了大量研究。但是目前绝大多数研究都是基于垂直型4H-SiC BJT,而对于平面型4H-SiC BJT击穿特性的研究相对较少。本论文对采取结终端扩展(JTE)和浮空场限环(FFLRs)两种基本结终端结构的平面型器件的击穿特性和击穿机理进行了比较和分析,并在此基础上进行了器件结构优化设计。     

Triple-push oscillator approach: theory and experiments

This paper presents the theory and experiments of the triple-push oscillator approach. This oscillator architecture is combined with three identical oscillator subcircuits. An analytical mode analysis is used to describe the behavior of all modes. As will be shown, odd-mode currents in each oscillator subcircuit have a 120° phase shift to one another and thus produce in-phase combining for the third harmonic. The time domain analysis was performed to simulate a triple-push oscillator, showing that the phenomenon of 120° phase shift exists among each oscillator subcircuit. To prove this concept, a 4.9-GHz hybrid bipolar junction transistor (BJT) circuit and a 28.4-GHz heterojunction bipolar transistor (BJT) MMIC chip were demonstrated. The measured results showed that the 4.9-GHz BJT triple-push oscillator delivered an output power of 1.0 dBm at 4.9 GHz with 12.0-dB fundamental rejection, and the 28.4-GHz HBT MMIC chip exhibited a measured center frequency at 28.4 GHz with an output power of -15.4 dBm, while the output powers of the fundamental and the second harmonic signals were suppressed to -21 and -34 dBm     

硅微波功率DMOSFET发展现状

简要地评述了硅微波功率ＤＭＯＳＦＥＴ （ＬＤＭＯＳ, ＶＤＭＯＳ） 的发展概况, 叙述了硅微波功率ＤＭＯＳ的基本结构和一些重要的制造技术。对微波功率ＤＭＯＳ的性能、特点与ＢＪＴ进行了比较, 并对其应用、发展方向及前景进行了探讨。