基于正反控制门的可逆网络化简

提出并证明正反控制(PNC)门级联电路中的合并、移动和分解规则,利用此规则给出基于PNC门的可逆网络的化简算法。根据移动规则对门序列进行正向和反向双向扫描,寻找符合化简条件的两门,直到可逆网络不发生变化为止。所有3变量可逆函数上的实验结果表明,该算法能减少PNC门级联网络的门数和控制位数,降低可逆网络的代价。     

基于正反控制门的可逆逻辑综合

提出一种基于正反控制(PNC)门可逆网络的级联算法,为3位输入/输出函数设计相应的模板,给出级联网络的约简算法。实验结果表明,与Toffoli门级联成的网络相比,使用PNC门的可逆网络中门的数量较少,在降低网络代价方面具有一定优势。     

基于相似函数与相似网络的可逆网络化简

提出了可逆函数的相似函数及可逆网络的相似网络,在此基础上构建了可逆网络化简方法。由可逆函数求出其所有的相似函数,对每个相似函数利用可逆逻辑综合算法生成可逆网络,再将其转换成对应的相似网络,并从中选取最优。该网络化简算法实现了生成三变量全部可逆函数和多变量可逆函数的可逆网络,与相关文献及Benchmark中的例题相比,构造可逆网络的门数较少,具有一定的优势。     

基于汉明距离递减变换的可逆逻辑综合算法

可逆逻辑综合是指对给定的可逆函数自动构造对应的可逆逻辑电路.现有的可逆逻辑综合算法虽然通过后期优化能够得到近似最优解,但是都存在生成的原始电路门数较多的问题,增加了后期优化工作的难度.文中提出一种基于真值表异位数计算的综合方法,根据异位数判定是否需增加逻辑非门达到减少输入和输出向量的汉明距离,从而实现边计算边简化函数,最后采用汉明距离递减变换的方法生成最终的电路.通过实验表明,相比于其他的综合算法,该算法得到的原始电路更接近于最优解或近似最优解,很大程度上减少了算法后续的优化工作量.     

基于位运算的量子可逆逻辑电路快速综合算法

量子可逆逻辑电路是构建量子计算机的基本单元.本文结合可逆逻辑电路综合的多种算法,根据可逆逻辑电路综合的本质是置换问题,巧妙应用位运算构造高效完备的Hash函数,提出了基于Hash表的新颖高效的量子可逆逻辑电路综合算法,可使用多种量子门,以极高的效率生成最优的量子可逆逻辑电路,从理论上实现制造量子电路的成本最低.按照国际同行认可的3变量可逆函数测试标准,该算法不仅能够生成全部最优电路,而且运行速度远远超过其它算法.实验结果表明,该算法按最小长度标准综合电路的平均速度是目前最好结果的69.8倍.     

类选择排序的可逆逻辑综合算法

可逆逻辑综合是指对给定的可逆函数自动构造对应的可逆逻辑电路.由于搜索空间随电路规模增长成指数增长,现有的可逆逻辑综合算法虽然能够得到近似最优的解,但是都存在计算时间过长的问题.文中提出了一种类似选择排序的可逆逻辑综合算法,其实质为基于变换规则的合成法.它采用一个无向无权图表示所有可以进行变换的路径,在综合的过程中,采用选择排序思想每次从小到大的选择需要交换的输出项,然后从路径选择图中找到最优的路径进行变换,最终使得函数的输出序列有序即完成综合.此外,文中还对得到的量子电路进行了优化.实验表明,相比其它综合算法,该算法不仅总能获得最优解或近似最优解,而且效率高、易于实现.     

基于Hash表的量子可逆逻辑电路综合的快速算法

量子可逆逻辑电路是构建量子计算机的基本单元,通过量子门的级联与组合构成量子计算机,量子可逆逻辑电路的综合就是根据电路功能,以较小的量子代价自动构造量子可逆逻辑电路.结合可逆逻辑电路综合的多种算法,提出了一种新颖高效的量子电路综合算法,巧妙构造最小完备的Hash函数,可使用多种量子门,采用任意量子代价标准,以极高的效率生成最优的量子可逆逻辑电路.为实现量子电路综合的自动化,首次提出了利用量子线的置换自动构造各种量子门库的通用算法.采用国际同行认可的3变量可逆函数测试标准,该算法不仅能够生成全部最优电路.而且运行速度远远超过其他算法·实验结果表明,该算法按最小长度、最小代价标准综合电路的平均速度分别是目前最好结果的49.15倍、365.13倍.     

基于关联选择的可逆逻辑综合算法

可逆逻辑综合是可逆计算的重要内容,为了解决可逆逻辑综合中可逆电路构造和优化问题,提出一种基于关联选择的可逆逻辑综合算法及相应的优化算法.将可逆函数用真值表表示,按真值表从上往下的顺序综合,并若干相关联变量作为综合的目标位,分别计算相对混乱度和绝对混乱度,以最小混乱度原则选取可逆逻辑门.该算法及其优化算法的时间复杂度为O(n2×2n),空间复杂度为O(n×2n),优于最佳算法的空间复杂度O(2n!).通过C++语言实现对3变量全部函数及部分4变量函数的综合,并与其他可逆逻辑综合算法的结果及benchmark范例比较,结果表明平均门数均具有一定优势.     

基于带权有向图的可逆逻辑综合改进算法

为减少可逆逻辑综合中使用的可逆门,通过对基于带权有向图的可逆逻辑综合算法的分析,针对函数转换过程中过渡门数较多及电路优化算法简单的问题,提出了有效的等复杂度基本输出变换的概念,扩充并证明了Toffoli门序列的移动和化简规则,给出了改进的基于带权有向图的可逆逻辑综合算法。实验结果表明,该算法不仅减少了可逆电路构成时所使用的可逆门,而且对构建的可逆电路实现了有效化简,大幅度减少了门数和控制位数,降低了可逆电路代价。     

基于正反控制模型的可逆逻辑综合

对一般Toffoli门进行了衍变和推广,给出了一个正反控制可逆级联模型(PNCRC),该模型拥有五种基本线型,并能正反控制目标位的输出.基于该模型给出了相应的可逆综合算法.对输入数不大于16的NCMCBench-mark函数进行测试并与已有的可逆综合方法比较,结果表明,利用该模型进行的可逆综合,垃圾信息数和可逆门数的优化效果都具有一定程度的改善.     

量子可逆逻辑综合的关键技术及其算法

最优化量子可逆逻辑的关键在于用最小的量子代价自动构造量子可逆逻辑.为了提高可逆逻辑自动生成与优化的效率,提出了类模板技术和一种快速算法.模板技术是一个有效的优化工具,类模板技术可以显著提高模板技术的匹配效率;R-M算法是可逆逻辑综合的一种较好的迭代方法,基于R-M算法的原始思想,构造了一个Hash函数,并在此基础上提出了一种可逆逻辑综合的快速算法.实验结果表明,在同等实验环境下使用类模板技术与快速算法,其优化的效果与效率远远优于已知的其他算法.     

基于卡诺图的三变量可逆逻辑综合算法

提出了一种基于卡诺图的可逆逻辑综合算法,该算法可以快速地求解带垃圾位的可逆逻辑综合问题。大量特定的可逆逻辑门都不可避免地带有一定的垃圾位, 如果使用真值表、置换群等经典可逆逻辑综合算法求解这些带垃圾位的可逆逻辑门,则因无法获得全局状态而很难得到结果。根据卡诺图的特点,将可逆逻辑问题分解为多个变量分别求解,无需关心全局状态。提出的卡诺图可逆逻辑综合算法 根据在卡诺图上的邻接性将3变量可逆逻辑问题划分为5个等价类;对每个等价类分别进行计算,在常数时间内解决了带垃圾位的可逆逻辑综合问题。     

Algebraic Characterization of Reversible Logic Gates

Reversible logic plays an important role in quantum computing. This paper investigates the universality and composition power of various known and new reversible gates. We present the algebraic characterization of selected new families of Boolean reversible gates. Some theoretical results on the relation between reversible w*w gates and the corresponding symmetric group are derived. Different combinations of reversible gate classes are proven to generate the entire class of reversible w*w gates.     

Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra

One of the elementary operations in computing systems is multiplication. Therefore, high-speed and low-power multipliers design is mandatory for efficient computing systems. In designing low-energy dissipation circuits, reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity. This paper introduces an efficient signed/unsigned 4 × 4 reversible Vedic multiplier with minimum quantum cost. The Vedic multiplier is considered fast as it generates all partial product and their sum in one step. This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output. First, the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam (UT) Sutra. This multiplier consists of bitwise multiplication and adder compressors. Compared with Vedic multipliers in the literature, the proposed design has a quantum cost of 111 with a reduction of 94% compared to the previous design. It has a garbage output of 30 with optimization of the best-compared design. Second, the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers. Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters. DesignI has separate binary two’s complement (B2C) and MUX circuits, while DesignII combines binary two’s complement and MUX circuits in one circuit. DesignI shows the lowest quantum cost, 231, regarding state-of-the-art. DesignII has a quantum cost of 199, reducing to 86.14% of DesignI. The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.     

Reversible logic-based magnitude comparator (RMC) circuit using modified-GDI technique for motion detection applications in image processing

Reversible or information lossless gates have applications in nano-technology, digital signal processing (DSP), communication, computer graphics and cryptography. Gate-diffusion input (GDI) technique can provide the possibility of designing fundamental gates in ultra-low power and layout chip area with low number of transistors. A reversible logic-based single-bit magnitude comparator (RMC) circuit is presented by using the modified-GDI (m-GDI) method-based reversible gates for designing RMC in any arbitrary number of bit levels for processing at nano-scales.In this paper, several figure of merits (FOMs) like: energy consumption-propagation delay product (EDP) and worst delay-power consumption-chip area product (DPA) are evaluated and compared with other designs. The simulation results show the improvement of the evaluation parameters of the proposed RMC in compare with the other similar basic GDI-based comparators. Also, according to the simulation results, presented comparator is capable to work at extensive frequency ranges with higher maximum operating frequency (f_max.). The effects of different process, voltage and the temperature (PVT) variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed circuit is robust against PVT variations and also noise-tolerable parameter.Moreover, the proposed RMC architecture is used in images applications. The results show that output images of the proposed inexact RMC have a very high quality and resemblance to the images generated by exact RMC, thus excellent values for the peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM) indicate that the proposed inexact RMC circuit has a proper accuracy for applications such as: comparative analysis in medical images, motion detector, edge detection and segmentation in nano-technology. Therefore, using the proposed scheme can be improved in comparator circuit in chips for future generation of VLSI and ULSI blocks, like: nano-processors performance.     

Reversible Computer Hardware

Conventional logic gates (e.g. AND gates) cannot be used for building a reversible computer. An appropriate design approach is necessary. Both small building blocks and a more complex circuit in MOS technology are presented. Today, these are useful in low-power digital electronics. Tomorrow, these may be useful in quantum computers.