Dynamic Power Supply Current Testing of CMOS SRAMs

We describe the design and implementation of a dynamic power supply current sensor which is used to detect SRAM faults such as disturb faults as well as logic cell faults. A formal study is presented to assess the parameters that influence the sensor design. The sensor detects faults by detecting abnormal levels of the power supply current. The sensor is embedded in the SRAM and offers on-chip detectability of faults. The sensor detects abnormal dynamic current levels that result from circuit defects. If two or more memory cells erroneously switch as a result of a write or read operation, the level of the dynamic power supply current is elevated. The sensor can detect this elevated value of the dynamic current. The dynamic power supply current sensor can supplement the observability associated with any test algorithm by using the sensor as a substitute for the read operations. This significantly reduces the test length and the additional observability enhances defect coverages.     

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.     

An Experimental 0.8 V 256‐kbit SRAM Macro with Boosted Cell Array Scheme

This work presents a low‐voltage static random access memory (SRAM) technique based on a dual‐boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read‐out current. A 0.18 µm CMOS 256‐kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 µW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.     

Implementation of low-voltage static RAM with enhanced data stability and circuit speed

This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.     

基于WO_x阻变材料的RRAM电路设计

采用HHNEC0.18μm标准CMOS工艺设计实现了多个1kb容量的阻变存储器电路。针对WOx阻变材料的操作特点,提出了可切换的写电路以及自调节的读参考电路,满足了单极(Unipolar)与双极(Bipolar)兼容操作需求的同时提高了读操作的成功率。引入位线限流模块解决了置位(set)过程需要字线限流的问题,进而可以实现包含‘0’和‘1’多位数据的并行写入。芯片采用高低两种电压设计,同时包含多种阵列尺寸结构的对比测试电路。     

AC-and DC-powered subnanosecond 1-kbit Josephson cache memorydesign

The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators     

A survey of circuit innovations in ferroelectric random-accessmemories

This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its contents for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip and the device imperfections of ferroelectric capacitors. We review six methods of generating a reference voltage, two being presented for the first time in this paper. These methods are discussed and evaluated in terms of their accuracy, area overhead and sensing complexity. Ferroelectric memories share architectural features such as addressing schemes and input/output circuitry with other types of random-access memories such as dynamic random-access memories. However, they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. We review nine different architectures for ferroelectric memories and discuss them in terms of speed, density and power consumption     

A Composite Circuit Model for NDR Devices in Random Access Memory Cells

Devices exhibiting negative differential resistance (NDR), such as resonant tunneling diodes and Esaki-type diodes, offer the promise of converting a dynamic random access memory (DRAM) cell to operate like a static random access memory cell with potentially lower dynamic power dissipation and faster read and write operations than a conventional DRAM. However, a circuit model that describes the operation of the resulting novel memory cell and is of use for both hand analysis and design, and circuit simulation as has yet been developed due to the non-analytical current-voltage curve of the two NDR devices in the cell. In this paper, a "composite" circuit model is presented that describes the relationship between current and voltage at the common node of connection of the two NDR devices. The composite model is analytical and can easily be implemented in SPICE or any circuit simulator. It is also useful for hand analysis of the read/write performance metrics. Finally, comparisons of composite models are presented     

Hybridization of CMOS With CNT-Based Nano-Electromechanical Switch for Low Leakage and Robust Circuit Design

Exponential increase in leakage power has emerged as a major barrier to technology scaling. Existing circuit techniques for leakage reduction either suffer from reduced effectiveness at nanometer technologies or affect performance and gate-oxide reliability. In this paper, we propose application of a specific carbon nanotube (CNT)-based nano-electromechanical switch as a leakage-control structure in logic and memory circuits. In case of memory circuits, we demonstrate that the proposed hybridization can be employed to reduce both cell leakage and bitline leakage, thereby improving the read noise margin as well. Due to the unique electromechanical properties of CNTs, these switches have high current-carrying capacity, extremely low leakage current, and low operating voltages. Moreover, they can act as nonvolatile memory elements, which can be exploited for data retention of important registers and latches during power down. Simulation results for a set of benchmark circuits show that we can obtain several orders of magnitude improvement in leakage saving in logic circuits at iso-performance compared to existing multi-threshold CMOS technique. In memory circuits, simulations show reduction in standby leakage and reduction in bitline leakage compared with the best existing techniques.     

An asynchronous GaAs MESFET static RAM using a new current mirrormemory cell

An experimental 1-kb GaAs MESFET static RAM using a new memory cell has been designed, fabricated and tested. The new memory cell is not subject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselected bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access current for readout than is possible using a conventional memory cell of the same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test circuit. A cell area of 350 μm² and cell current of 60 μA were achieved using a conventional E/D process     

Printed Organic One‐Time Programmable ROM Array Using Anti‐fuse Capacitor

This paper proposes printed organic one‐time programmable read‐only memory (PROM). The organic PROM cell consists of a capacitor and an organic p‐type metal‐oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store “0.” Some organic PROM cells are programmed to “1” by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16‐bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with –50 V, and they are read out with –20 V. The area of the 16‐bit organic PROM array is 70.6 mm².     

Self-convergent scheme for logic-process-based multilevel/analog memory

A multilevel/analog electrically erasable programmable read only memory cell fabricated by standard CMOS logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE subcircuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications.     

Board-level built-in self-repair method of RAM

This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM’s faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algorithm to find out failure memory units and replace the faulty units with FPGA. Then it can build a memory that has no fault concern to external controller, and realizes the logic binding between external controller and RAM. Micro Controller Unit (MCU) can operate external RAM correctly even if RAM has some fault address units. Conventional MCS-51 is used to simulate the operation of MCU operating external memory. Simulation shows FPGA can complete the faulty address units’ mapping and MCU can normally read and write external RAM. This design realizes the RAM’s built-in self-repairing on board.     

A ferroelectric-piezoelectric random access memory

A two-dimensional ferroelectric memory array is combined with a piezoelectric interrogation technique to provide a memory device with nonvolatile storage, random access, non-destructive readout and compatibility with integrated circuits. Binary information is stored as either a positive or negative polarization state in ferroelectric ceramic material and is read out by sensing the polarity of the piezoelectric response of the material. Calculations and experimental results are presented for a 5 word × 5 bits per word prototype device for which a complete logic and driving circuit has been designed and used. Switching characteristics, disturb pulse sensitivity, and changes with temperature are presented. Calculations show that word-to-word capacitive coupling will affect the maximum size of the memory and will probably limit the number of words per chip to approximately 25. No such limit exists on the number of bits per word.     

一种相变存储器读出电路及其快速读出方法

针对大规模相变存储器所具有的寄生电容大、可能出现读破坏现象等特性,提出了一种读电压模式的相变存储器读出电路及其快速读出方法。基于SMIC 40nm CMOS工艺的仿真结果表明,在2.5V电源电压下,该方法可以在90ns的读出周期内正确读出位线寄生电容为30pF的存储单元数据,同时,该读出周期随位线寄生电容的减小而减小。另外,该方法可以和传统的Burst等快速读出方式并存,非常适用于带数据预读机制的高端存储器技术。     

A current direction sense technique for multiport SRAM's

This paper describes two techniques for low-power single-end multiport SRAMs: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal, When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%     

Static random access memory using high electron mobility transistors

A 4-bit fully decoded static random access memory (RAM) has been designed and fabricated using high electron mobility transistors (HEMT's) with a direct-coupled FET logic approach. The circuit incorporates approximately 50 logic gates. A fully operating memory circuit was demonstrated with an access time of 1.1 ns and a minimum WRITE-enable pulse of less than 2-ns duration at room temperature. This memory consumes a total power of 14.89 mW and 87.8 µW per memory cell.     

Algorithmic analogue-to-quaternary convertor circuit using current-mode CMOS

A new current-mode CMOS algorithmic analogue-to-quaternary data convertor circuit has been realised in a standard polysilicon-gate CMOS technology. This circuit accepts an analogue current input and develops a set of quaternary, base-four, output currents. A single type of convertor cell may be cascaded to the desired number of quaternary output digits. The reference current that defines the full scale input range may be set externally. This circuit is input-output compatible with other previously described VLSI-compatible current-mode CMOS quaternary threshold logic and memory circuits.<>     

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 klogic gates and on-chip test circuitry

A soft-error-immune, 0.9-ns address access time, 2.0-ns read/write cycle time, 1.15-Mb emitter coupled logic (ECL)-CMOS SRAM with 30-ps 120 k ECL and CMOS logic gates has been developed using 0.3-μm BiCMOS technology. Four key developments ensuring good testability, reliability, and stability are on-chip test circuitry for precise measurement of access time and for multibit parallel testing, a memory-cell test technique for an ECL-CMOS SRAM, a highly stable current source with a simple design using a current mirror, and a soft-error-immune memory cell using a silicon-on-insulator (SOI) wafer. These techniques will be especially useful for making the ultrahigh-speed, high-density SRAM's used as cache and control storages in mainframe computers     

Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit

A new multi-valued static random access memory (MVSRAM) cell with a hybrid circuit consisting of a single-electron (SE) and MOSFETs is proposed. The previously reported MVSRAM with an SE-MOSFET hybrid circuit needs two data lines, one bit line for write operations and one sense line for read operations, to improve the speed of the read-out operation, but the proposed cell has only one data line for read/write operations, resulting in a memory area that is much smaller than that of the previous cell, without any reduction of read-out speed.