Three-dimensional discrete wavelet transform architectures

The three-dimensional (3-D) discrete wavelet transform (DWT) suits compression applications well, allowing for better compression on 3-D data as compared with two-dimensional (2-D) methods. This paper describes two architectures for the 3-D DWT, called the 3DW-I and the 3DW-II. The first architecture (3DW-I) is based on folding, whereas the 3DW-II architecture is block-based. Potential applications for these architectures include high definition television (HDTV) and medical data compression, such as magnetic resonance imaging (MRI). The 3DW-I architecture is an implementation of the 3-D DWT similar to folded 1-D and 2-D designs. It allows even distribution of the processing load onto 3 sets of filters, with each set performing the calculations for one dimension. The control for this design is very simple, since the data are operated on in a row-column-slice fashion. Due to pipelining, all filters are utilized 100% of the time, except for the start up and wind-down times. The 3DW-II architecture uses block inputs to reduce the requirement of on-chip memory. It has a central control unit to select which coefficients to pass on to the lowpass and highpass filters. The memory on the chip will be small compared with the input size since it depends solely on the filter sizes. The 3DW-I and 3DW-II architectures are compared according to memory requirements, number of clock cycles, and processing of frames per second. The two architectures described are the first 3-D DWT architectures     

基于DSP Builder的二维提升小波变换实现

离散小波变换在图像压缩处理中有着重要的作用,并得到了广泛的应用.与传统的基于卷积的架构相比较,基于提升的架构具有需要较少的硬件资源,占用较少的芯片面积等优点.在DSP Builder中实现了基于提升的一维离散小波变换,并通过构造相关的存储器控制逻辑,完成了二维离散小波变换架构的设计.利用该架构对图像进行离散小波变换,与软件变换的结果相比较,并计算出图像的峰值信噪比,验证了其正确性.     

Efficient architectures for two-dimensional discrete wavelet transform using lifting scheme.

Novel architectures for 1-D and 2-D discrete wavelet transform (DWT) by using lifting schemes are presented in this paper. An embedded decimation technique is exploited to optimize the architecture for 1-D DWT, which is designed to receive an input and generate an output with the low- and high-frequency components of original data being available alternately. Based on this 1-D DWT architecture, an efficient line-based architecture for 2-D DWT is further proposed by employing parallel and pipeline techniques, which is mainly composed of two horizontal filter modules and one vertical filter module, working in parallel and pipeline fashion with 100% hardware utilization. This 2-D architecture is called fast architecture (FA) that can perform J levels of decomposition for N * N image in approximately 2N2(1 - 4(-J))/3 internal clock cycles. Moreover, another efficient generic line-based 2-D architecture is proposed by exploiting the parallelism among four subband transforms in lifting-based 2-D DWT, which can perform J levels of decomposition for N * N image in approximately N2(1 - 4(-J))/3 internal clock cycles; hence, it is called high-speed architecture. The throughput rate of the latter is increased by two times when comparing with the former 2-D architecture, but only less additional hardware cost is added. Compared with the works reported in previous literature, the proposed architectures for 2-D DWT are efficient alternatives in tradeoff among hardware cost, throughput rate, output latency and control complexity, etc.     

Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform

This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs). The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other 2-D DWT structures require a fixed memory size.     

An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000

In this paper, we propose an efficient pipeline architecture for the DWT 9/7 filter defined in JPEG 2000. The proposed architecture is composed of column and row processors to perform the separable 2-D DWT. Based on the rescheduling DWT algorithm, we derive a new data flow graph to shorten the critical path. The proposed 1-D column processor requires less pipeline registers to achieve about the same critical path compared with other lifting-based architectures. For the row processor, the data dependency of each lifting step is reduced to only two computation nodes and therefore more pipeline registers can be applied to achieve higher processing speed without increasing the internal memory size in the 2-D case. That is, for an N × N image, it only requires 4N internal memory to perform the row-wise transform. For the memory bit-width analysis, we use software simulation to reduce the memory bit-width for various compression ratios. Since a portion of information from least significant bits of DWT coefficients would be discarded after EBCOT-tier2 processing, one can decrease the data width of internal memory to perform various compression ratios of JPEG 2000 coding, especially at the low-bit rates. Our simulation results suggest that it is practically possible to design the energy-aware memory architecture to further reduce the power consumption in the future work.     

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera’s C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.     

一种基于提升的二维离散小波变换VLSI架构

离散小波变换(Discrete Wavelet Transform,DWT)需要较多的运算量以及较大的存储器空间,为了使之适用于实时的图像处理应用,就需要开发特殊的架构和芯片来提高离散小波变换的运算性能。基于提升的二维DWT提出了一种新型的VLSI结构——LLSP架构,其结合逐级和基于行的架构这两者特点,带来了硬件开销和存储器空间的降低,并可以用于多提升步骤的扩展以及多级二维离散小波变换。     

Multiview image coding using depth layers and an optimized bit allocation

In this paper, we present a novel wavelet-based compression algorithm for multiview images. This method uses a layer-based representation, where the 3-D scene is approximated by a set of depth planes with their associated constant disparities. The layers are extracted from a collection of images captured at multiple viewpoints and transformed using the 3-D discrete wavelet transform (DWT). The DWT consists of the 1-D disparity compensated DWT across the viewpoints and the 2-D shape-adaptive DWT across the spatial dimensions. Finally, the wavelet coefficients are quantized and entropy coded along with the layer contours. To improve the rate-distortion performance of the entire coding method, we develop a bit allocation strategy for the distribution of the available bit budget between encoding the layer contours and the wavelet coefficients. The achieved performance of our proposed scheme outperforms the state-of-the-art codecs for several data sets of varying complexity.     

Discrete wavelet transform: data dependence analysis and synthesisof distributed memory and control array architectures

We perform a thorough data dependence and localization analysis for the discrete wavelet transform algorithm and then use it to synthesize distributed memory and control architectures for its parallel computation. The discrete wavelet transform (DWT) is characterized by a nonuniform data dependence structure owing to the decimation operation it is neither a uniform recurrence equation (URE) nor an affine recurrence equation (ARE) and consequently cannot be transformed directly using linear space-time mapping methods into efficient array architectures. Our approach is to apply first appropriate nonlinear transformations operating on the algorithm's index space, leading to a new DWT formulation on which application of linear space-time mapping can become effective. The first transformation of the algorithm achieves regularization of interoctave dependencies but alone does not lead to efficient array solutions after the mapping due to limitations associated with transforming the three-dimensional (3-D) algorithm onto one-dimensional (1-D) arrays, which is also known as multiprojection. The second transformation is introduced to remove the need for multiprojection by formulating the regularized DWT algorithm in a two-dimensional (2-D) index space. Using this DWT formulation, we have synthesized two VLSI-amenable linear arrays of LPEs computing a 6-octave DWT decomposition with latencies of M and 2M-1, respectively, where L is the wavelet filter length, and M is the number of samples in the data sequence. The arrays are modular, regular, use simple control, and can be easily extended to larger L and J. The latency of both arrays is independent of the highest octave J, and the efficiency is nearly 100% for any M with one design achieving the lowest possible latency of M     

Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.     

基于改进的K-L变换的多光谱图像压缩算法

融合离散小波变换(DWT,discrete wavelet tran sform)与Karhunen-Loeve变换(KLT),将图像的能量集中到少数系数上,以达到更好的 压缩效果。首先将多光谱图像的每个谱段进行快速9/72D DWT,消除多光谱图像的大部分 空间冗余;然后对所有谱段产生的小波系数进行改进的KLT,来消除光谱冗余和残存的空 间冗余;最后对所得谱段产生的小波系数进行改进的KLT,来消除光谱冗余和残存的空间冗 余;最后对所得系数进行熵编码,得到压缩码流。实验结果表明,在码率为0.25～2.0bit/ pixel范围内,平均信噪比(SNR)高于41dB,同时缩短了运 算时间,从而提升了多光谱图像压 缩算法的性能。     

小波图像编码的硬件实现

设计了二维离散小波变换和快速零树编码的硬件结构,实现了一小波图像编码系统.编写了各个模块的Verilog HDL模型,并进行了仿真和逻辑综合.最后用Altera公司的CPLD对整个编码系统进行了验证.结果表明,设计的硬件结构是正确的,可以用来实现小波图像编码系统.     

Architectures for wavelet transforms: A survey

Wavelet transforms have proven to be useful tools for several applications, including signal analysis, signal compression and numerical analysis. This paper surveys the VLSI architectures that have been proposed for computing the Discrete and Continuous Wavelet Transforms for 1-D and 2-D signals. The architectures are based upon on-line versions of the wavelet transform algorithms. These architectures support single chip implementations and are optimal with respect to both area and time under the word-serial model.     

A fast Discrete Wavelet Transform algorithm for visual processing applications

For visual processing applications, the two-dimensional (2-D) Discrete Wavelet Transform (DWT) can be used to decompose an image into four-subband images. However, when a single band is required for a specific application, the four-band decomposition demands a huge complexity and transpose time. This work presents a fast algorithm, namely 2-D Symmetric Mask-based Discrete Wavelet Transform (SMDWT), to address some critical issues of the 2-D DWT. Unlike the traditional DWT involving dependent decompositions, the SMDWT itself is subband processing independent, which can significantly reduce complexity. Moreover, DWT cannot directly obtain target subbands as mentioned, which leads to an extra wasting in transpose memory, critical path, and operation time. These problems can be fully improved with the proposed SMDWT. Nowadays, many applications employ DWT as the core transformation approach, the problems indicated above have motivated researchers to develop lower complexity schemes for DWT. The proposed SMDWT has been proved as a highly efficient and independent processing to yield target subbands, which can be applied to real-time visual applications, such as moving object detection and tracking, texture segmentation, image/video compression, and any possible DWT-based applications.     

用于空间转换的巴克ISAR信号形成与图像重构

讨论了基于巴克相位编码调制发射信号和三维逆合成孔径雷达（ISAR）结构的ISAR概念。ISAR信号形成可理解为3D图像功能向2D信号功能的非对称空间转换,而图像重构被认为是2D信号功能向2D图像功能（重构的图像）的空间逆转换。经证实,这种图像重构算法由距离压缩互相关、方位压缩傅里叶变换（被认为是第一级运动补偿）和更高级相位校正组成（被认为是更高级运动补偿,通称自聚焦程序）。引入熵作为图像成本功能,以评估相位校正功能的多项式系数。通过数值实验以验证ISAR的几何结构,信号形成模式和图像重构算法。     

9/7提升小波变换图像处理算法的高速FPGA实现

提升结构(Lifting Scheme)是一种新的双正交小波变换构造方法.这种方法使得计算复杂度大大降低,有效地减少了运行时间.介绍了基于FPGA的高速9/7提升小波变换的设计,提出采用多级流水线硬件结构实现一维离散小波变换(1-D DWT).该结构使系统吞吐量提高到原来的3倍,面积仅增加40%.在实现二维离散小波变换(2-D DWT)时采用基于行的结构,可以提高片内资源利用率和运行速度,满足小波变换实时性的要求.     

A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform

Many VLSI architectures for computing the discrete wavelet transform (DWT) were presented, but the parallel input data sequence and the programmability of the 2-D DWT were rarely mentioned. In this paper, we present a parallel-processing VLSI architecture to compute the programmable 2-D DWT, including various wavelet filter lengths and various wavelet transform levels. The proposed architecture is very regular and easy for extension. To eliminate high frequency components, the pixel values outside the boundary of the image are mirror-extended as the symmetric wavelet transform (SWT) and the mirror-extension is realized via the routing network. Owing to the property of the parallel processing, we adopt the row-based recursive pyramid algorithm (RPA), similar to 1-D RPA, as the data scheduling. This design has been implemented and fabricated in a 0.35 m 1P4M CMOS technology and the working frequency is 50 MHz. The chip size is about 5200 m × 2500 m. For a 256 × 256 image, the chip can perform 30 frames per second with the filter length varying from 2 to 20 and with various levels. The proposed architecture is suitable for real-time applications such as JPEG 2000.     

基于小波变换的数字水印应用

伴随着网络技术扣多媒体技术的飞速发展，数字媒体给人们带来极大便利的同时，也面临着严峻的挑战，版权保护扣信息安全成为一个迫在眉睫的现实问题。数字水印技术作为版权保护扣信息安全的重要手段得到了广泛的研究扣应用，他通过在原始数据中嵌入秘密信息——水印来证实该数据的所有权或完整性，达到版权保护扣信息安全的目的．本文基于人类视觉系统(HVS)的特性，提出了一种小波变换域的数字水印算法，将水印图像嵌入到小波变换的不同方位的重要系数当中，文中实现了标志图像水印．实验结果表明，该水印算法对图像处理扣压缩等运算有较强的鲁棒性。     

Multiview video compression with 1-D transforms

Many alternative transforms have been developed recently for improved compression of images, intra prediction residuals or motion-compensated prediction residuals. In this paper, we propose alternative transforms for multiview video coding. We analyze the spatial characteristics of disparity-compensated prediction residuals, and the analysis results show that many regions have 1-D signal characteristics, similar to previous findings for motion-compensated prediction residuals. Signals with such characteristics can be transformed more efficiently with transforms adapted to these characteristics and we propose to use 1-D transforms in the compression of disparity-compensated prediction residuals in multiview video coding. To show the compression gains achievable from using these transforms, we modify the reference software (JMVC) of the multiview video coding amendment to H.264/AVC so that each residual block can be transformed either with a 1-D transform or with the conventional 2-D Discrete Cosine Transform. Experimental results show that coding gains ranging from about 1–15% of Bjontegaard-Delta bitrate savings can be achieved.     

Efficient realizations of the discrete and continuous wavelettransforms: from single chip implementations to mappings on SIMD arraycomputers

This paper presents a wide range of algorithms and architectures for computing the 1D and 2D discrete wavelet transform (DWT) and the 1D and 2D continuous wavelet transform (CWT). The algorithms and architectures presented are independent of the size and nature of the wavelet function. New on-line algorithms are proposed for the DWT and the CWT that require significantly small storage. The proposed systolic array and the parallel filter architectures implement these on-line algorithms and are optimal both with respect to area and time (under the word-serial model). Moreover, these architectures are very regular and support single chip implementations in VLSI. The proposed SIMD architectures implement the existing pyramid and a'trous algorithms and are optimal with respect to time