深亚微米抗辐射加固设计的SPICE仿真验证方法

由于在抗辐射加固设计(RHBD)中采用了环形栅的版图结构,由此引发了直栅SPICE仿真验证方法对RHBD不适用的问题.通过分析深亚微米工艺技术下环形栅结构的特性,建立了环形栅的有效栅宽长比算法,同时构建了环形栅的SPICE仿真模型,并针对抗辐射加固设计提出了如何有效地提取版图参数网表的策略,从而解决了传统SPICE仿真验证对RHBD不适用的问题,通过有效的仿真验证,确保电路性能,提高设计的可靠性.     

输入光波长变化对DPE厚环输出效果的影响

在已设计并实验实现了氦氖 6 32 8nm高斯光束输入环输出的 16阶衍射相位元件 (DPE)基础上 ,模拟了与设计不同的输入光的波长对DPE整形效果的影响 ;利用与设计DPE波长不同的半导体激光器 (波长为 6 6 0nm)进行了实验研究。结果表明 :在DPE与输出平面的间隔 (L 值 )始终为设计值时 ,当输入光波长处于 6 30～ 6 37nm范围内 ,环上均匀性的均方误差SE不大于 1% ;当输入波长与L值满足L =L0 ×λ0 /λ′时 ,波长在 6 32 8± 37(nm)的范围内 ,环上均匀性的均方误差SE不大于 1% ,实验结果与理论模拟基本相吻合。     

PDSOI SRAM单元的单粒子加固方法

通过MEDICI的二维器件模拟,提出不仅在正栅下的体区受到单粒子入射后释放电荷外,漏极也可以在受到单粒子入射后释放干扰电荷.对SOI SRAM单元中器件的漏极掺杂浓度进行优化,可以减小漏极受到单粒子入射所释放的电荷.改进了SOI SRAM的单元结构,可以提高SRAM抗单粒子翻转(SEU)的能力.     

采用CFD方法对液氮冷却结构进行流体和热分析

低温应用的大功率器件需要设计高冷却效率的液冷室结构。采用计算流体动力学（CFD）方法模拟了以液氮-氮气两相流为制冷剂的空腔结构、微通道结构和扰流柱结构的流动与传热过程。结果表明,相比于空腔结构和微槽道结构,扰流柱结构具有较好的换热能力。圆形扰流柱易发展45°方向支流,而方形扰流柱结构有利于垂直方向流速均匀化。相较于平行排布,扰流柱交错排列时圆形和方形扰流柱结构中流速分布更为均匀。对比对流换热系数发现,交错排布优于平行排布,方形扰流柱优于圆形扰流柱。换热效果最好的结构为交错排布的2 mm方形扰流柱,对流换热系数为4223 W/(m2·K),较空腔结构提高125.83%。采用上述结构进行测试验证,在107.6 W加热功率工况下冷头测温点温度与相同功率下仿真结果有较好的对应性。     

用正向栅控二极管的方法对场效应晶体管的参数提取

本文用正向栅控二极管的方法来提取场效应晶体管的栅氧层厚度和体掺杂浓度,尤其是在这两个变量事先都未知的情况下进行提取。首先,用器件物理推导出了以栅氧层厚度、体掺杂浓度为参数的正向栅控二极管峰值电流。然后用ISE-Dessis模拟了不同栅氧层厚度和体衬底掺杂浓度下的产生复合电流峰值的特性,用于参数提取。模拟数据的结果与正向栅控二极管的方法显示出高度的一致性。     

Open-Silicon采用Magma的SiliconSmart ACE进行标准单元和I／O单元特征化与建模

Magma公司近日宣布，Open-Silicon公司采用SiliconSmartACE作为标准单元和I／O单元特征化与建模标准工具。作为SiliconSmart的长期用户，OpenSilicon升级用了SiliconSmartACE，充分利用了该工具公认快速精确的多个工艺、电压和温度（PVT）角点库特征化的能力，     

工件形状对激光相变硬化温度场和应力场的影响

利用Sysweld有限元软件建立三维有限元模型,采用三维高斯热源,考虑材料热物性能随温度的变化,对平板和回转体内壁进行了激光相变硬化数值模拟。分析了温度场、残余应力以及马氏体分布的异同,研究了工件形状对激光相变硬化温度场和残余应力的影响规律。结果表明,在表层方向上,平板模型和回转体内壁模型的热循环相似;截面方向上,内壁模型峰值温度高于平板模型。处理后相变区组织均主要以马氏体为主,其体积分数约为90%。相变区边缘及热影响区产生残余拉应力,相变区存在残余压应力;与内壁模型相比,平板模型相变区中心残余压应力数值较大。     

使用Monte Carlo方法对光子-物质的相互作用进行模拟

在医学影像获得方法中，核医学与传统的放射线探测，扫描仪探测，核磁共振相比，是唯一能获得器官功能性信息的方法，但它获得的图像质量不如其他方法。开发了一种图像探测仪并使用Monte Carlo方法对其各组成部分进行模拟从而可以通过调整参数来获得高分辨的图像。     

采用ECR-PEMOCVD方法进行立方和六方GaN单晶薄膜生长的准热力学模型和相图

基于热力学平衡理论,对在电子回旋共振等离子体增强金属有机化学气相沉积系统中的Ga N薄膜生长给出了一个化学平衡模型.计算表明,Ga N生长的驱动力Δp是以下生长条件的函数: 族输入分压,输入 / 比,生长温度.计算了六方和立方Ga N的生长相图,计算结果和我们的实验结果显示出一定的一致性.通过分析,解释了高温和高 / 比生长条件适合六方Ga N的原因.上述模型可以延伸到用于Ga N单晶薄膜生长的类似系统中.     

数值方法和计算参数对束传播方法精度影响的研究

本文参聚合物方向耦合器为对象,研究了二维ＢＰＭ和三维ＢＭＰ在模拟工方面的差别以及剖分点数、传播步长、初始有效折射率等计算参数对精度的。在研究过程中,利用有效折射率的方法,把三维波导转化为二维波导,分别采用三维ＢＰＭ和二维ＢＰＭ进行了模拟,并对模拟结果进行了模拟,并对模拟结果进行了比较,发现二者符合很好,表明二维ＢＭＰ具有很高的工。研究还表明初台有效折射率、传播步长的取值对模拟结果影响不明显,部分点     

一个基于C单元双重冗余的65纳米工艺抗辐射触发器

A radiation-hardened flip-flop is proposed to mitigate the single event upset(SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.     

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.     

新型带清零的半静态D触发器芯片设计

为了提高D触发器的速度、降低功耗、缩小面积,本文对常用D触发器进行分析,综合各自优缺点,优化最高频率,设计出一款新型带清零的半静态D触发器,采用华润上华0.6μmN阱CMOS工艺,版图面积为46.500×40.350(μm)。该触发器的最高频率为356MHz,运用她构成二分频器并仿真成功。     

Low-power level converting flip-flop with a conditional clock technique in dual supply systems

Clustered voltage scaling (CVS) is an effective way to reduce power consumption in digital integrated circuits. Level-converting flip-flops are the critical elements in the CVS scheme. In this paper a single edge implicit pulse-triggered level-converting flip-flop with a conditional clock technique (CC-LCFF) is proposed and proved to be suitable for use in low-power non-critical paths with Dual-VDD. CC-LCFF conditionally blocks the clock signal when the input data does not make any transition, so the redundant transitions of internal nodes are eliminated and the total power consumption is reduced. Based on the SMIC 65 nm technology, the post-layout simulation results show that the proposed CC-LCFF shows an improvement of 69.41–72.40% in power consumption and 23.36–47.73% in power-delay product (PDP) as compared with its counterparts.     

Oxygen incorporation in TiN for metal gate work function tuning with a replacement gate integration approach

In this study, we used oxygen to increase the work function of a TiN gated stack. To prevent the EOT growth associated with oxygen incorporation, we proposed a novel replacement gate flow, where oxygen incorporation by O₂ anneal on a thin TiN layer was performed after dopant activation. With this novel flow, a maximum work function tuning range of ∼0.32 eV was achieved without significant EOT penalty, making it attractive for p-type metal gate integration.     

一种新型的快速关断绝缘栅双极晶体管

本文提出了一种新型的快速关断绝缘栅双极晶体管。在关断的时候,器件用一个自己驱动的P型晶体管来短路发射极PN结。在没有引入如折返电流电压曲线等副作用和工艺困难的情况下,器件实现了低导通压降和快速关断。数值仿真表明关断时间从120ns降到12纳秒,同时并没有增加导通压降。     

TTL主从JK触发器在CP脉冲升降沿的工作特性研究

TTL主从JK触发器在时钟脉冲下降沿会出现输出状态异变，本文对这一问题进行了研究。     

基于Zernike环多项式的环孔径波面拟合方法

波面拟合分析是干涉测量技术中数据处理以得到所需信息和结果的一个重要环节。提出了一种通用的圆和环孔径波面拟合分析方法,选用在单位环域里正交的Zernike环多项式为拟合基函数。对比分析结果不仅表明了所提出方法的有效性和通用性,而且显示出该方法可解决通常的基于Zernike圆多项式干涉图处理软件在拟合分析环孔径波前时存在的问题。     

Electrical performance study of 25 nm Ω-FinFET under the influence of gamma radiation: A 3D simulation

In this research paper, a 3D process simulation of 25 nm n-channel Ω-FinFET and the effect of Gamma radiation on device characteristics have been studied. Device simulations are carried out under the influence of Gamma radiation under varying does conditions from 100 Krad (SiO₂) to 10 Mrad (SiO₂). Effects of Gamma radiation on the threshold voltage, transfer characteristics, drive current, off-state leakage current and subthreshold characteristics have been studied. Extracted parameters for virgin and irradiated devices have been compared in order to understand the degradation in the electrical characteristics of the Ω-FinFET under study. Simulation results under the low drain and high drain bias has been reported and discussed. It is found that Ω-FinFET delivers better performance under irradiation as compared with conventional single gate MOS structures. Ω-FinFET is shown to be significantly tolerant to gamma radiation upto dose of 5 Mrad (SiO₂). In addition, the influence of quantum effects on this nanoscale device is investigated in detail. Sentaurus simulation results obtained has been compared with the reported experimental data.