Analog Circuit Fault Detection Using Location of Poles

A method for detection of parametric faults occurring in linear analog circuits based on location of poles of the Circuit Under Test (CUT) is proposed. In the proposed method, the value of each component of the CUT is varied within its tolerance limit using monte carlo simulation. The upper and lower bounds of magnitude, phase angle, real part and imaginary part of all poles of the CUT are obtained. While testing, the locations of poles are obtained. If any one or more of the poles lies outside the tolerance limit then the CUT is declared faulty. The effectiveness of the proposed method is validated through two benchmark circuits like second order sallenkey band pass filter and fourth order leapfrog low pass filter.     

Fault Detection of Analog Circuits Using Network Parameters

A new method to detect component faults in analog circuits is proposed in this paper. Network parameters like driving point impedance, transfer impedance, voltage gain and current gain are used to detect component faults in analog circuits as these network parameters are sensitive to the components of the circuit. Using montecarlo simulation each component of the circuit is varied within its tolerance limit and the minimum and the maximum values of each network parameter are found for fault free circuit. At the time of testing, the network parameters are found for the injected fault and if any one or more network parameters is exceeding its predetermined bound limits then the circuit is confirmed faulty. The proposed method is validated through second order Sallenkey band pass filter and fourth order Chebyshev low pass filter circuits. Numerical results are presented to clarify the proposed method and prove its efficiency.     

Test‐Generation‐Based Fault Detection in Analog VLSI Circuits Using Neural Networks

In this paper, we propose a novel test methodology for the detection of catastrophic and parametric faults present in analog very large scale integration circuits. An automatic test pattern generation algorithm is proposed to generate piece‐wise linear (PWL) stimulus using wavelets and a genetic algorithm. The PWL stimulus generated by the test algorithm is used as a test stimulus to the circuit under test. Faults are injected to the circuit under test and the wavelet coefficients obtained from the output response of the circuit. These coefficients are used to train the neural network for fault detection. The proposed method is validated with two IEEE benchmark circuits, namely, an operational amplifier and a state variable filter. This method gives 100% fault coverage for both catastrophic and parametric faults in these circuits.     

Soft Fault Classification of Analog Circuits Using Network Parameters and Neural Networks

A new method to identify component faults in analog circuits is proposed using network parameters like driving point impedance, transfer impedance, voltage gain and current gain. Using Monte-Carlo simulation each component of the circuit is varied within its tolerance limit and samples of each network parameter are found for fault free circuit. Similarly all possible single faults are introduced and the corresponding samples of network parameters are found. Fault classification is done through neural network. The proposed method is validated through second order Sallenkey band pass filter. Numerical results are presented to clarify the proposed method and prove its efficiency.     

Analog Circuits Fault Detection Using Cross-Entropy Approach

This paper presents a novel method that can detect component faults in analog circuits. Because the probability density function (PDF) of output voltage (current) is sensitive to the components of the circuit, the cross-entropy between the good circuit and the bad circuit is employed to detect component faults in analog circuits based on the autoregressive (AR) model. In the proposed approach, the value of each component of the circuit undertest (CUT) is varied within its tolerance limit using Monte Carlo simulation. The minimal and maximal bounds of the cross-entropy are found for fault-free circuit. While testing, the cross-entropy is obtained. If cross-entropy lies outside the tolerance limit then the CUT is declared faulty. The effectiveness of the proposed method is demonstrated via the second order Sallenkey bandpass filter circuit and continuous-time low pass state-variable filter circuit.     

Fault Diagnosis of Linear Analog Electronic Circuit Based on Natural Response Specification using K-NN Algorithm

This paper reports a novel method for parametric fault diagnosis in linear analog electronic circuits using distance weighted cosine K-Nearest Neighbours (K-NN) algorithm that performs data classification on the basis of cosine similarity between data features or attributes. In this approach the analog electronic Circuit Under Test (CUT) is represented in the form of a transfer function model and natural response specifications of the system such as damping ratio, natural frequency and static gain of the system are extracted as features from this model. For experimentation purpose a second order Sallen-Key band pass filter and a fourth order Chebychev Type 1 low pass filter is considered, the corresponding fault classes are created for each of the circuit. The parameter values of the passive components in the system have been varied to derive the features, and each component whose tolerance varied is labelled with a corresponding fault class. The proposed methodology classifies faulty classes with accuracy greater than 95%.

     

Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing

Semiconductor testing is aimed at screening fabrication defects that impact expected functionality. While catastrophic defects result in non working devices, parametric faults result in marginalities and are of increasing concern with deep sub-micron process technologies. This work presents a scheme to monitor Circuit-Under-Test (CUT) static bias current to identify catastrophic as well as parametric faults. All circuits require a deterministic amount of DC bias current which may vary outside the specifications when faults exist within the circuit. We propose a compensated current measurement Built-in-Current-Sensor (BICS) scheme, which can be used for sub-system level/circuit-level bias current measurements. The BICS provides accessibility to internal blocks and enables isolated parametric testing. Calibration routine enables process independence and provides robustness. The BICS is compatible with Very-Low-Cost Automatic Test Equipment (VLC-ATE), and can be used for detailed parametric testing in the production environment.     

Third-order voltage-mode active-C band pass filter

In this research article, a new third-order voltage-mode active-C asymmetrical band pass filter is proposed. It uses three numbers of current-controlled current conveyors and three numbers of equal-valued capacitors. The topology has the following important features: uses only three active elements, uses three capacitors, uses all grounded capacitors and no resistor is suitable for integrated circuit design, there is no matching constraint, high input impedance, low output impedance, central frequency can easily be electronically controlled by bias current, and frequency response is asymmetrical in nature. The application of the proposed topology in the realisation of a voltage-mode sixth-order symmetrical band pass filter has been demonstrated. The workability of the proposed topology and sixth-order filter has been confirmed by simulation results using 0.35-µm Austria Micro Systems complementary metal oxide semiconductor technology.     

Implicit functional testing of switched current filter based on fault signatures

This article aims at defining an efficient test strategy for switched-current (SI) circuit testing. By checking the constructed signatures (impulse response samples) against the derived tolerance ranges, we can infer the correctness of the device under test without explicitly measuring the original performance parameters. We also describe a technique of mapping the tolerance ranges in the performance space to its associated tolerance ranges in the signature space (We call such a procedure implicit functional testing). Taking into account the specificity of SI circuit, catastrophic and parametric fault model for testing are constructed. A fifth order Butterworth low-pass filter and a sixth order Elliptic band-pass filter have been used as test benches to assess the effectiveness of the proposed technique. Test results demonstrate that high fault coverage can be achieved with low cost test equipments.     

Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor

This paper presents a test method based on the analysis of the dynamic power supply current, both quiescent and transient, of the circuit under test. In an off-chip measurement, the global interconnect impedance associated with the chip package and the test equipment and, also, the chip input/output cells will complicate the extraction of the information provided by the current waveform of the circuit under test. Thus, the supply current is measured on-chip by a built-in current sensor integrated in the die itself. To avoid the effective reduction of the voltage supply, the measurement is performed in parallel by replicating the current that flows through selected branches of the analog circuit. With the aim of reducing the test equipment requirements, the built-in current sensor output generates digital level pulses whose width is related to the amplitude and duration of the circuit current transients. In this way the defective circuit is exposed by comparing the digital signature of the circuit under test with the expected one for the fault-free circuit. A fault evaluation has been carried out to check the efficiency of the proposed test method. It uses a fault model that considers catastrophic and parametric faults at transistor level. Two benchmark circuits have been fabricated to experimentally verify the defect detection by the built-in current sensor. One is an operational amplifier; the other is a structure of switched current cells that belongs to an analog-to-digital converter.     

基于信息融合技术的模拟电路故障诊断

论述了基于多类电量测试信息模糊融合的模拟电路故障诊断方法的基本原理,提出了分别基于K故障节点诊断法和最小标准差法的元件故障隶属函数构造方法,以及基于可测点电压与不同测试频率下电路增益的模糊信息融合诊断算法.分别利用此两类测试信息及K故障诊断法和最小标准差法,对电路进行初步诊断,再运用模糊变换及故障定位规则,得到融合的故障诊断结果.模拟实验结果表明,所提方法大大提高了故障定位的准确率.     

Test of a switched-capacitor ADC by a built-in charge sensor

A test methodology for switched capacitor circuits is described. The test approach uses a built-in sensor to analyze the charge transfer inside the circuit under test (CUT). The test methodology is applied to a 10-bit algorithmic analog to digital converter to obtain the static linearity and to the simulated fault coverage figures taking into account a catastrophic fault model. The goodness of the charge sensor has been experimentally evaluated with an SC integrator for fault detection and built-in sensor influence on the CUT performance.     

Analogue fault detectability comparison between power supply current and output voltage magnitude and phase spectrum components

A method using magnitude and phase spectrum components for fault detection of catastrophic and parametric faults is presented. A procedure is developed, discrimination factors are defined and their values are adjusted to include circuit parameter deviations. Comparative results from linear and nonlinear configurations of operational amplifier circuits are given, showing a significant increase in fault detectability over a previous method and also an improvement in fault coverage by the use of the power supply current against the output voltage signal.     

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.     

X波段SICL小型化带通滤波器的设计

为有效减小X波段滤波器的尺寸,减小通带损耗,对基片集成同轴线(SICL)结构进行了研究,提出一种阶跃阻抗(SIR)型SICL带通滤波器,并针对SICL谐振腔与其他平面电路的连接设计了一种由共面波导(CPW)向SICL谐振腔提供激励的平面结构,以便滤波器的测量。仿真结果表明,滤波器通带特性优异,其中心频率为10 GHz,带宽为1.5 GHz,尺寸为13 mm×7 mm,插入损耗为-0.8 dB。     

Performance analysis of a low power low noise tunable band pass filter for multiband RF front end

This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.     

Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis

In this work a strategy for testing analog networks, known as Transient Response Analysis Method, is applied to test the Configurable Analog Blocks (CABs) of Field Programmable Analog Arrays (FPAAs). In this method the Circuit Under Test (CUT) is programmed to implement first and second order blocks and the transient response of these blocks to known input stimuli is analyzed. Taking advantage of the inherent programmability of the FPAAs, a BIST-based scheme is used in order to obtain an error signal representing the difference between fault-free and faulty CABs. Two FPAAs from different manufacturers and distinct architectures are considered as CUT. For one of the devices there is no detailed information about its structural implementation. For this reason, a functional fault model based on high-level parameters of the transfer function of the programmed blocks is adopted, and then, the relationship between these parameters and CAB component deviations is investigated. The other considered device allows a structural programming in which the designer can directly modify the values of programmable components. This way, faults can be injected by modifying the values of these components in order to emulate a defective behavior. Therefore, it is possible to estimate the fault coverage and test application time of the proposed functional test method when applied to both considered devices.

Nth order current mode universal filter using MOCCCIIs

This article presents a new current mode single-input-multiple-output nth order universal filter. The proposed circuit employs (n + 1) number multiple output second generation current conveyors and n number grounded capacitors only. Presented circuits can realize current mode low pass, high pass, band pass, notch and all pass responses simultaneously at different high output impedance terminals. The current mode filter circuit provides low input impedance by selecting the proper value of bias current and also has high output impedance, which is suitable for cascading. The circuit offers some important features such as resistor less realization, no passive component matching constraints, low sensitivity, electronic tunability and active-C realization. The functionality of the proposed filter circuit is tested with the PSPICE simulation, which is found to agree well with the proposed theory.     

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.     

窄带LC带通滤波器的设计与实现

为适应现代舰载电子战设备对低频滤波器的严格要求,通过对传统带通滤波器的结构进行适当的网络变换,得到了一种可靠的电路结构。该结构将原有集总参数带通网络的电路元件参数值转化成常见量值,同时最大程度地吸收了集总元件的寄生参数,使滤波器的性能更加稳定。测试结果表明：采用该结构的滤波器具有很窄的带宽、较高的阻带抑制度以及优良的电...