A design for testability approach for nano-CMOS analogue integrated circuits

Dependability requirements must be considered from the beginning when designing safety-critical systems. Therefore, testing should even be considered earlier, intertwined with the design process. The process of designing for better testability is called design for testability (DfT). This article presents two designs for testability and fault diagnosis techniques using a new design analogue checker circuit in order to improve the testability and the diagnosability of nano-CMOS (complementary metal oxide semiconductor) analogue circuits used in safety-critical applications based on the system-on-chip (SoC) approach design. The testing techniques presented in this work can be done during and after the system fabrication. The checker is implemented in full-custom 65 nm Complementary metal–oxide–semiconductor (CMOS) technology with low supply voltage and small-size capabilities. SPICE simulations of the post-layout extracted CMOS checker, which include all parasitic, are used to validate the technique and demonstrate the acceptable electrical behaviour of the checker.     

Computational analysis and comparison of reversible gates for design and test of logic circuits

Quantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL（能量回收电容耦合逻辑）,该电路的能耗低于传统CMOS电路及其他能量回收电路．ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑．同时ERCCL是一种阈值逻辑．所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗．针对ERCCL提出了一种阈值逻辑综合方法．用基准电路集MCNC做了相应的实验．与SIS的综合结果相比,该方法大约减少80％的逻辑门．     

能量回收电容耦合逻辑及其综合方法

提出了一种新型能量回收电路ERCCL(能量回收电容耦合逻辑),该电路的能耗低于传统CMOS电路及其他能量回收电路.ERCCL利用电容耦合进行逻辑求值,因此可以在一个门中低能耗地实现高扇入、高复杂度的逻辑.同时ERCCL是一种阈值逻辑.所以一个基于ERCCL的系统可以大大减少逻辑门数,从而降低系统能耗.针对ERCCL提出了一种阈值逻辑综合方法.用基准电路集MCNC做了相应的实验.与SIS的综合结果相比,该方法大约减少80%的逻辑门.     

能量回收阈值逻辑电路

通过把阈值逻辑应用在能量回收电路中,提出了一种新的电路形式——能量回收阈值逻辑电路(energyre-coverythresholdlogic,ERTL).阈值逻辑的应用,使ERTL电路的门复杂度大大降低,同时进一步降低了功耗.分别以ERTL电路和静态CMOS电路设计了4位超前进位加法器,两个加法器采用相同的结构.ERTL加法器逻辑电路的晶体管数目只占静态CMOS加法器的63%,与现有的能量回收电路相比,硬件开销减少.设计使用的是TSMC0.35μm工艺,分别在3V和5V工作电压下对电路进行Spice仿真.仿真结果显示,在实际的工作负载和工作频率范围内,ERTL电路的能耗只有静态CMOS电路的14%～58%     

CMOS电路的最大动态功耗计算和测试生成＊

本文首先提出,CMOS电路的最大动态功耗计算,可以通过计算在特定输入序列作用下电路中的不变门数的最小值来实现。本文提出的极性推导、赋值法可以快速求解不变门数的最小值,并生成相应的输入序列。该算法与电路的输入变量数无关。     

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively.     

A Novel Method for Power Analysis Based on Combinational Logic in Block Cipher Circuit

In this paper, we propose a method that builds power model template according to input transi- tions of combinatorial logic circuit. By computing its cor- relation with the overall power consumption of a crypto- graphic circuit, we are able to recover the secret key. Sev- eral simulation-based experiments have been conducted, which verifies the feasibility of our method and shows that the combinatorial logic is also faced with the problem of information leakage in power analysis cases. Compared with DPA （Differential power analysis） and CPA （Corre- lation power analysis）, our attack is fairly effective against the cryptographic circuits whose protection is only imple- mented on the register parts of the sequential circuit. In addition, a few topics for further research, as well as the ad- vices for more precise power model and countermeasures, are presented at the end of the paper.     

DECISION OF OPTIMAL HOPFIELD NEURAL NETWORK MODEL OF COMBINATIONAL CIRCUITS

By use of Hopfield model and basis solution of homogeneous linear equations which are established in accordance with consistent state, a practical decision method for the existence of optimal Hopfield model of combinational circuits is provided. Finally, an example is given.     

组合电路最优Hopfield模型的判定

采用组合电路Hopfield模型,通过相容状态建立的齐次线性方程组的基础解系,提出了组合电路最优Hopfield模型存在性的实用判定方法,并给出了计算实例。     

Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.     

Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

Advances in nano-electronics VLSI manufacturing technology and the rapid downscaling of the size of logic circuits have made them more prone to errors. This has led to the need for fast circuit reliability evaluation of large logic circuits. In this paper a new method for reliability analysis of VLSI logic circuits based on a modified form of Mason’s rule is proposed. Utilizing matrix sparsity significantly increases the speed and reduces the required memory of the proposed approach. In addition, an approach is introduced to mitigate the effect of reconvergent paths. Simulation results indicate that the proposed method is scalable and runs 4× faster than previously proposed schemes.     

“数字电路与逻辑设计”课程实验改革

＂数字电路与逻辑设计＂课程传统的实验教学在实验室进行,教师难于指导众多学生。我们制作便携式实验板,将实验器材发放给学生,让学生在课外自主实验,可以提高学生实践能力。新型实验讲义把实验指导和空白实验报告整合在一起,可以节约学生撰写实验报告的时间。     

Accelerating hybrid and compact neural networks targeting perception and control domains with coarse-grained dataflow reconfiguration

Driven by continuous scaling of nanoscale semiconductor technologies,the past years have witnessed the progressive advancement of machine learning techniques and applications.Recently,dedicated machine learning accelerators,especially for neural networks,have attracted the research interests of computer architects and VLSI designers.State-of-the-art accelerators increase performance by deploying a huge amount of processing elements,however still face the issue of degraded resource utilization across hybrid and non-standard algorithmic kernels.In this work,we exploit the properties of important neural network kernels for both perception and control to propose a reconfigurable dataflow processor,which adjusts the patterns of data flowing,functionalities of processing elements and on-chip storages according to network kernels.In contrast to stateof-the-art fine-grained data flowing techniques,the proposed coarse-grained dataflow reconfiguration approach enables extensive sharing of computing and storage resources.Three hybrid networks for MobileNet,deep reinforcement learning and sequence classification are constructed and analyzed with customized instruction sets and toolchain.A test chip has been designed and fabricated under UMC 65 nm CMOS technology,with the measured power consumption of 7.51 mW under 100 MHz frequency on a die size of 1.8×1.8 mm^2.     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTL PLA与普通结构的PLA相比,包括功率时钟电路的功耗在内,ERTL PLA仍节省65%～77%的功耗.     

能量回收阈值逻辑及其功率时钟产生电路

提出了能量回收阈值逻辑电路(ERTL).该电路把阈值逻辑应用到绝热电路中,降低能耗的同时也降低了电路的门复杂度.并且提出了一种高效率的功率时钟产生电路.该功率时钟电路能够根据逻辑的复杂度和工作频率,调整电路中MOS开关的开启时间,以取得最优的能量效率.为了便于功率时钟的优化设计,推导出了闭式结果.基于0.35μm的工艺参数,设计并且仿真了ERTL可编程逻辑阵列(PLA)和普通结构PLA.在20～100MHz的工作频率范围内,提出的功率时钟电路的能量效率可以达到77%～85%.仿真结果还显示,ERTL是一个低能耗的逻辑.ERTLPLA与普通结构的PLA相比,包括功率时钟电路的     

Finding Minimum Energy Disjoint Paths in Wireless Ad-Hoc Networks

We develop algorithms for finding minimum energy disjoint paths in an all-wireless network, for both the node and link-disjoint cases. Our major results include a novel polynomial time algorithm that optimally solves the minimum energy 2 link-disjoint paths problem, as well as a polynomial time algorithm for the minimum energy k node-disjoint paths problem. In addition, we present efficient heuristic algorithms for both problems. Our results show that link-disjoint paths consume substantially less energy than node-disjoint paths. We also found that the incremental energy of additional link-disjoint paths is decreasing. This finding is somewhat surprising due to the fact that in general networks additional paths are typically longer than the shortest path. However, in a wireless network, additional paths can be obtained at lower energy due to the broadcast nature of the wireless medium. Finally, we discuss issues regarding distributed implementation and present distributed versions of the optimal centralized algorithms presented in the paper.Anand Srinivas is currently a PhD candidate in the Laboratory for Information and Decision Systems (LIDS) at MIT. He recieved his Masters of Science in EECS from MIT in 2004, and his Bachelors of Applied Science in Computer Engineering from the University of Toronto in 2001. In 2004 he also received a Masters of Science in Aerospace Engineering from MIT. His current research interests include reliability and energy-efficiency in wireless ad-hoc networks, routing and network optimization, graph theory, and the design of efficient algorithms. E-mail: anand3@mit.eduEytan Modiano received his B.S. degree in Electrical Engineering and Computer Science from the University of Connecticut at Storrs in 1986 and his M.S. and Ph.D. degrees, both in Electrical Engineering, from the University of Maryland, College Park, MD, in 1989 and 1992 respectively. He was a Naval Research Laboratory Fellow between 1987 and 1992 and a National Research Council Post Doctoral Fellow during 1992–1993 while he was conducting research on security and performance issues in distributed network protocols.Between 1993 and 1999 he was with the Communications Division at MIT Lincoln Laboratory where he designed communication protocols for satellite, wireless, and optical networks and was the project leader for MIT Lincoln Laboratory’s Next Generation Internet (NGI) project. He joined the MIT faculty in 1999, where he is presently an Associate Professor in the Department of Aeronautics and Astronautics and the Laboratory for Information and Decision Systems (LIDS). His research is on communication networks and protocols with emphasis on satellite, wireless, and optical networks.He is currently an Associate Editor for Communication Networks for IEEE Transactions on Information Theory and for The International Journal of Satellite Communications. He had served as a guest editor for IEEE JSAC special issue on WDM network architectures; the Computer Networks Journal special issue on Broadband Internet Access; the Journal of Communications and Networks special issue on Wireless Ad-Hoc Networks; and for IEEE Journal of Lightwave Technology special issue on Optical Networks. He is the Technical Program co-chair for Wiopt 2006 and vice- chair for Infocom 2007. E-mail: modiano@mit.edu     

A method for defining analog circuits for the minimization of discrete functionals: An image processing application

The solutions of many physical-mathematical problems can be obtained by minimizing proper functionals. In the literature, some methods for the synthesis of analog circuits (mainly cellular neural networks) are presented that find the solution of some of these problems by implementing the discretized Euler-Lagrange equations associated with the pertinent functionals.In this paper, we propose a method for defining analog circuits that directly minimize (in a parallel way) a class of discretized functionals in the frequently occurring case where the solution depends on two spatial variables. The method is a generalization of the one presented in Parodi et al.,Internat. J. Circuit Theory Appl., 26, 477–498, 1998. The analog circuits consist of both a (nonlinear) resistive part and a set of linear capacitors, whose steady-state voltages represent the discrete solution to the problem. The method is based on the potential (co-content) functions associated with voltage-controlled resistive elements. es an example, we describe an application in the field of image processing: the restoration of color images corrupted by additive noise.This work was supported by the M.U.R.S.T. research project, Neural and non-linear circuits for one- and multi-dimensional signal processing applications, and by the University of Genoa.     

An efficient design of embedded memories and their testability analysis using Markov chains

This article presents a design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM) where neither are the address, read/write and data input lines directly controllable nor are the data output lines externally observable. Unlike the conventional approaches, which frequently employ on-chip circuits such as linear feedback shift register (LFSR), data registers and multibit comparator for verifying the response of the memory-under-test (MUT) with the reference signature of a fault-free gold unit, the proposed technique uses an efficient testable design, which helps accelerate test algorithms by a factor of 0.5n, if the RAM is organized into an n×1 array and improve the test reliability by eliminating the LFSR that is known to have aliasing problems. Another serious problem in embedded memory testing by random test patterns is the problem of memory initialization, which has been tackled here by adding word-line flag registers. The paper has made indepth empirical studies of the functional faults such as stuck-at, coupling, and pattern-sensitive by suitably representing these faults by Markov chains and by simulating these chains to derive various test lengths required for detecting these faults. The simulation results conclusively show that, in order to test a IM-bit RAM for detecting the common functional faults, the proposed technique needs only one second as opposed to about an hour needed by the conventional random testing where memory cells are tested sequentially.An abridged version of this article was published in the IEEE International Conference on Wafer-Scale Integration, January 1989. This research was partially supported by the NSF under grant number MIP-9013092 and by ONR under grant number 85-K-0716.