一种FPGA抗辐射布线算法设计

随着集成密度的增大以及工作电压的降低,基于SRAM的FPGA芯片更加容易受到单粒子翻转的影响。提出了一种基于通用布局布线工具VPR的抗辐射布线算法,通过改变相关布线资源节点的成本函数,来减少因单粒子翻转引起的桥接错误,并与VPR比较下板测试结果。实验结果表明,该布线算法可以使芯片的容错性能提升20%左右,并且不需要增加额外的硬件资源或引入电路冗余。     

A CASE tool for software architecture design

This paper describes the Software Architect's Assistant, an automated visual tool for the design and construction of Regis distributed programs. Unlike conventional CASE tools and their supported methodologies, the Architect's Assistant supports a compositional approach to program development in which the software architecture plays a central role throughout the software life-cycle—from the early design stage through to system management and evolution.In its implementation, we have addressed some of the limitations of existing CASE tools, particularly in the degree of automated support offered to the human developer. Conscious effort has been made to maximise usability and efficiency, primarily by enhancing the level of automation and flexibility together with careful design of the user interface. Our objective is to provide a tool which automates all mundane clerical tasks, enforces program correctness and consistency and, at the same time, accommodates the individual working styles of its users.Although currently specific to the development of Regis programs, the Architect's Assistant embodies concepts and ideas which are applicable to CASE tools in general.     

A tool for design pattern detection and software architecture reconstruction

It is well known that software maintenance and evolution are expensive activities, both in terms of invested time and money. Reverse engineering activities support the obtainment of abstractions and views from a target system that should help the engineers to maintain, evolve and eventually re-engineer it. Two important tasks pursued by reverse engineering are design pattern detection and software architecture reconstruction, whose main objectives are the identification of the design patterns that have been used in the implementation of a system as well as the generation of views placed at different levels of abstractions, which let the practitioners focus on the overall architecture of the system without worrying about the programming details it has been implemented with.In this context we propose an Eclipse plug-in called MARPLE (Metrics and Architecture Reconstruction Plug-in for Eclipse), which supports both the detection of design patterns and software architecture reconstruction activities through the use of basic elements and metrics that are mechanically extracted from the source code. The development of this platform is mainly based on the exploitation of the Eclipse framework and plug-ins as well as of different Java libraries for data access and graph management and visualization. In this paper we focus our attention on the design pattern detection process.     

A demand based route generation algorithm for public transit network design

This paper presents a public transit network route generation algorithm. The main contribution of this work is the introduction of new route generation algorithms. The proposed route generation algorithm is tested on Mandl׳s Swiss Road network and the four large networks presented in recent previous work. Three parameters are used to evaluate the route sets generated by the proposed algorithm. These are the zero transfer percentage, the average travel time, and the total route cost. The route sets generated for the large networks have better parameter values compared to recent previous work.     

Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs

This paper presents an architecture for the extraction of visual primitives on chip: energy, orientation, disparity, and optical flow. This cost-optimized architecture processes in real time high-resolution images for real-life applications. In fact, we present a versatile architecture that may be customized for different performance requirements depending on the target application. In this case, dedicated hardware and its potential on-chip implementation on FPGA devices become an efficient solution. We have developed a multi-scale approach for the computation of the gradient-based primitives. Gradient-based methods are very popular in the literature because they provide a very competitive accuracy vs. efficiency trade-off. The hardware implementation of the system is performed using superscalar fine-grain pipelines to exploit the maximum degree of parallelism provided by the FPGA. The system reaches 350 and 270 VGA frames per second (fps) for the disparity and optical flow computations respectively in their mono-scale version and up to 32 fps for the multi-scale scheme extracting all the described features in parallel. In this work we also analyze the performance in accuracy and hardware resources of the proposed implementation.     

A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention

Pattern matching is one of the most performance-critical components for the content inspection based applications of network security, such as network intrusion detection and prevention. To keep up with the increasing speed network, this component needs to be accelerated by well designed custom coprocessor. This paper presents a parameterized multilevel pattern matching architecture (MPM) which is used on FPGAs. To achieve less chip area, the architecture is designed based on the idea of selected character decoding (SCD) and multilevel method which are analyzed in detail. This paper also proposes an MPM generator that can generate RTL-level codes of MPM by giving a pattern set and predefined parameters. With the generator, the efficient MPM architecture can be generated and embedded to a total hardware solution. The third contribution is a mathematical model and formula to estimate the chip area for each MPM before it is generated, which is useful for choosing the proper type of FPGAs. One example MPM architecture is implemented by giving 1785 patterns of Snort on Xilinx Virtex 2 Pro FPGA. The results show that this MPM can achieve 4.3 Gbps throughput with 5 stages of pipelines and 0.22 slices per character, about one half chip area of the most area-efficient architecture in literature. Other results are given to show that MPM is also efficient for general random pattern sets. The performance of MPM can be scalable near linearly, potential for more than 100 Gbps throughput. Supported by the National Natural Science Foundation of China (Grant No. 60803002), and the Excellent Young Scholars Research Fund of Beijing Institute of Technology     

A model and software architecture for MMORPG traffic generation based on player behavior

In this paper we present a software architecture for traffic generation based on application level player behavior in Massively Multiplayer Online Role-Playing Games (MMORPGs). We have performed measurements of network traffic for each of the previously defined action categories for MMORPGs (Trading, Questing, Dungeons, Raiding, Player versus Player Combat, and Uncategorized), as well as measurements of application level player behavior in terms of listed action categories. Based on the obtained datasets we have created network traffic models for each action category and player behavior models with focus on hourly and daily trends. Network traffic models are implemented in Distributed Internet Traffic Generator and verified through comparison with the real traffic. Player behavior models explore number of active players, session duration, as well as lengths and probability of session segments (i.e., parts of the session consisting of only one category of player actions). We propose an architecture which enables scalable, behavior-driven traffic generation and implement it in a laboratory testbed. In order to achieve scalability of the system, we use Linux Containers as a virtualization technique. The resulting implementation can generate hundreds of MMORPG streams on a single PC. As a case study we used Activision Blizzard’s World of Warcraft.     

基于贪心算法和遗传算法的仓储车辆调度算法

针对仓储车辆调度问题提出一种基于贪心算法与遗传算法的调度算法。它主要利用遗传算法为框架筛选、进化出高效的调度方案,算法又融合了贪心算法对调度中的任务排序进行了快速优化。此融合使得遗传算法的编码简便,排除了不可行解的可能,从而使得算法性能大大提高。算法已经C++语言编程实现,实验分析证明:算法有效地提升了调度方案的效率。     

基于改进元胞多目标遗传算法的机床主轴优化

为了进一步提高元胞遗传算法在求解多目标优化问题时的收敛性和分布性。在多目标元胞遗传算法的基础上,引入了三维空间元胞,提出了三维元胞多目标遗传算法。采用多目标基准测试函数对该算法进行了测试,并将其与目前比较流行的几种多目标遗传算法进行对比。结果表明,此种算法在收敛性和分布性上取得了更好的效果。采用以上这几种算法分别对机床主轴多目标优化问题进行了求解,相比其他几种算法,改进的多目标元胞遗传算法得到了更优的结果,说明了改进的算法在求解此问题时行之有效。     

A data based algorithm for the generation of random vectors

We demonstrate an algorithm for generating random vectors based on a sample of observations of a multivariate random variable X. Although our goal is the generation of pseudo observations which behave as though they came from the underlying density of X, in the algorithm discussed, estimation of the underlying density is not required. Rather, the observations are combined using stochastic multipliers to generate simulated observations. Because of the local nature of the generation scheme, the algorithm requires few assumptions on the underlying density. The algorithm is intended for use in simulation studies in which a large number of nonrepeated pseudo observations are to be obtained from a relatively small set of experimental data.     

Five-axis tool path generation for a flat-end tool based on iso-conic partitioning

Traditionally, for the flat-end tool, due to the intertwined dependence relationship between its axis and reference point, most 5-axis tool-path generation algorithms take a decoupled two-stage strategy: first, the so-called cutter contact (CC) curves are placed on the part surface; then, for each CC curve, tool orientations are decided that will accommodate local and/or global constraints such as minimum local gouging and global collision avoidance. For the former stage, usually simplistic “offset” methods are adopted to determine the cutter contact curves, such as the iso-parametric or iso-plane method; whereas for the latter, a common practice is to assign fixed tilt and yaw angle to the tool axis regardless the local curvature information and, in the case of considering global interference, the tool orientation is decided solely based on avoiding global collision but ignoring important local machining efficiency issues. This independence between the placement of CC curves and the determination of tool orientations, as well as the rigid way in which the tilt and yaw angle get assigned, incurs many undesired problems, such as the abrupt change of tool orientations, the reduced efficiency in machining, the reduced finishing surface quality, the unnecessary dynamic loading on the machine, etc. In this paper, we present a 5-axis tool-path generation algorithm that aims at alleviating these problems and thus improving the machining efficiency and accuracy. In our algorithm, the CC curves are contour lines on the part surface that satisfy the iso-conic property — the surface normal vectors on each CC curve fall on a right small circle on the Gaussian sphere, and the tool orientations associated to a CC curve are determined by the principle of minimum tilt (also sometimes called lead) angle that seeks fastest cutting rate without local gouging. Together with an elaborate scheme for determining the step-over distance between adjacent CC curves that seeks maximum material removal, the presented algorithm offers some plausible advantages over most existing 5-axis tool-path generation algorithms, particularly in terms of reducing the angular velocity and acceleration of the rotary axes of the machine. The simulation experiments of the proposed algorithm and their comparison with a leading commercial CAM software toolbox are also provided that demonstrate the claimed advantages.     

一种基于MapReduce架构的并行矩阵Apriori算法

传统数据挖掘关联规则Apriori算法直接移植到云计算平台,数据挖掘效率虽然有了数量级的提升,但由于需要频繁地扫描事务数据库,增加了系统I/O、内存和通信的开销。提出一种基于矩阵的并行关联规则算法Apriori_MMR,该算法结合了数据划分的思想进行并行化改进,简化了生成候选项的连接步骤,仅需对事务数据库扫描两次,同时在计算过程中还能对事务进行压缩从而进一步提高了算法的性能。通过两种算法在不同数据规模下算法性能对比分析实验和两种算法在相同数据集不同节点数对比实验,共同验证了Apriori_MMR的运算效率至少要比Apriori_MR高出两倍左右,且设置的支持度阈值越小,效果愈明显。     

The design and implementation of a code generation tool

A practical approach to the development of a high-quality, re-usable code generator is described in this paper. This code generator produces code for the Prime 64V mode architecture, but the methodology used is generally applicable to the construction of compilers for most architectures. The code generator accepts a tree-structured intermediate form, linearized and represented as a file of integers. This intermediate form uses high-level operators, minimizing work by compiler front-ends that use it and providing a number of advantages in the code generation process. The output of the code generator is assembly language. This tool was found to considerably extend the capabilities of students in a graduate compiler class and has been used in the construction of Pascal and C compilers.     

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.     

A blackboard architecture for plastics design

Engineering design is a complex, ill-structured problem involving vast amounts of knowledge that often deal with incomplete, and uncertain, information. The design process typically involves a number of sub-tasks, some of which are amenable to numeric or algorithmic processing (e.g., analysis and optimization); most other sub-tasks require symbolic processing, and are typically solved by expert designers who rely on experiential knowledge used in the form of heuristics. The latter set of sub-tasks were chiefly responsible for creating the symbolic bottleneck that has set back the efforts to automate the design process. However, with the advent of recent AI methodologies we now have techniques for tackling the symbolic bottleneck. Even though some progress has been made in this area with the aid of knowledge-based expert systems, many important questions still remain to be research. In the DESIGNER project we are performing empirical studies that focus on these questions using the plastics design problem as our test bed. We have focused on the preliminary or the base-case design in this domain and have implemented a working prototype called DESIGNER, based on the blackboard architecture. This paper discusses the various aspects of DESIGNER, which is a hybrid, integrated, conferring expert system (HICEX). We are currently extending DESIGNER's capabilities to address the other aspects of the plastics design problem such as part design, plastics processing selection, etc. We are also investigating decentralized communication architectures for integrating multiple experts on the design problem.     

A program design language based software maintenance tool

Program design languages are an increasingly important method of expressing the detailed design of a software system. Such languages can be modelled using a data structure known as a semantic net. This paper describes a maintenance tool for program design languages based on such a data structure. The tool allows the user to interrogate a semantic net using an interactive procedural language in order to derive information necessary for software maintenance. The technique upon which this tool is based is applicable to the maintenance of activities throughout the software lifecycle.     

基于遗传算法的空间网格划分匿名算法

隐私泄露问题已经成为阻碍基于位置的服务（location-based services,LBS）进一步发展的原因。针对当LBS用户发送查询时,用户的个人隐私可能会泄露给攻击者的问题,提出了基于遗传算法的空间网格划分的隐私保护算法（GAGP）。算法包括两个方法,即地图分割算法和假名生成法。地图分割算法利用遗传算法给每个网格赋权值,再通过使用邻接网格扩展的方法,保证每个划分区域的查询频率基本相等。假名生成法是用户在每次发送查询时使用假名来应对长期统计的攻击方式。通过实验证明所提算法与其他三种算法相比结果较好,所以提出的方案能够有效地保护用户的隐私。     

Knowledge based quality-driven architecture design and evaluation

Modelling and evaluating quality properties of software is of high importance, especially when our every day life depends on the quality of services produced by systems and devices embedded into our surroundings. This paper contributes to the body of research in quality and model driven software engineering. It does so by introducing; (1) a quality aware software architecting approach and (2) a supporting tool chain. The novel approach with supporting tools enables the systematic development of high quality software by merging benefits of knowledge modelling and management, and model driven architecture design enhanced with domain-specific quality attributes. The whole design flow of software engineering is semi-automatic; specifying quality requirements, transforming quality requirements to architecture design, representing quality properties in architectural models, predicting quality fulfilment from architectural models, and finally, measuring quality aspects from implemented source code. The semi-automatic design flow is exemplified by the ongoing development of a secure middleware for peer-to-peer embedded systems.     

A parallel architecture for discrete relaxation algorithm

Discrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conventional hardware design for a Discrete Relaxation Algorithm (DRA) suffers from O(n2m3) time complexity and O(n2m2) space complexity. By reformulating DRA into a parallel computational tree and using a multiple tree-root pipelining scheme, time complexity is reduced to O(nm), while the space complexity is reduced by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm). Furthermore, a technique for dynamic configuring an architectural wavefront is used which leads to an O(n) time highly concurrent DRA3 architecture.     

A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Deep learning and, in particular, convolutional neural networks (CNN) achieve very good results on several computer vision applications like security and surveillance, where image and video analysis are required. These networks are quite demanding in terms of computation and memory and therefore are usually implemented in high-performance computing platforms or devices. Running CNNs in embedded platforms or devices with low computational and memory resources requires a careful optimization of system architectures and algorithms to obtain very efficient designs. In this context, Field Programmable Gate Arrays (FPGA) can achieve this efficiency since the programmable hardware fabric can be tailored for each specific network. In this paper, a very efficient configurable architecture for CNN inference targeting any density FPGAs is described. The architecture considers fixed-point arithmetic and image batch to reduce computational, memory and memory bandwidth requirements without compromising network accuracy. The developed architecture supports the execution of large CNNs in any FPGA devices including those with small on-chip memory size and logic resources. With the proposed architecture, it is possible to infer an image in AlexNet in 4.3 ms in a ZYNQ7020 and 1.2 ms in a ZYNQ7045.