A CASE tool for software architecture design

This paper describes the Software Architect's Assistant, an automated visual tool for the design and construction of Regis distributed programs. Unlike conventional CASE tools and their supported methodologies, the Architect's Assistant supports a compositional approach to program development in which the software architecture plays a central role throughout the software life-cycle—from the early design stage through to system management and evolution.In its implementation, we have addressed some of the limitations of existing CASE tools, particularly in the degree of automated support offered to the human developer. Conscious effort has been made to maximise usability and efficiency, primarily by enhancing the level of automation and flexibility together with careful design of the user interface. Our objective is to provide a tool which automates all mundane clerical tasks, enforces program correctness and consistency and, at the same time, accommodates the individual working styles of its users.Although currently specific to the development of Regis programs, the Architect's Assistant embodies concepts and ideas which are applicable to CASE tools in general.     

A tool for design pattern detection and software architecture reconstruction

It is well known that software maintenance and evolution are expensive activities, both in terms of invested time and money. Reverse engineering activities support the obtainment of abstractions and views from a target system that should help the engineers to maintain, evolve and eventually re-engineer it. Two important tasks pursued by reverse engineering are design pattern detection and software architecture reconstruction, whose main objectives are the identification of the design patterns that have been used in the implementation of a system as well as the generation of views placed at different levels of abstractions, which let the practitioners focus on the overall architecture of the system without worrying about the programming details it has been implemented with.In this context we propose an Eclipse plug-in called MARPLE (Metrics and Architecture Reconstruction Plug-in for Eclipse), which supports both the detection of design patterns and software architecture reconstruction activities through the use of basic elements and metrics that are mechanically extracted from the source code. The development of this platform is mainly based on the exploitation of the Eclipse framework and plug-ins as well as of different Java libraries for data access and graph management and visualization. In this paper we focus our attention on the design pattern detection process.     

Pipelined architecture for real-time cost-optimized extraction of visual primitives based on FPGAs

This paper presents an architecture for the extraction of visual primitives on chip: energy, orientation, disparity, and optical flow. This cost-optimized architecture processes in real time high-resolution images for real-life applications. In fact, we present a versatile architecture that may be customized for different performance requirements depending on the target application. In this case, dedicated hardware and its potential on-chip implementation on FPGA devices become an efficient solution. We have developed a multi-scale approach for the computation of the gradient-based primitives. Gradient-based methods are very popular in the literature because they provide a very competitive accuracy vs. efficiency trade-off. The hardware implementation of the system is performed using superscalar fine-grain pipelines to exploit the maximum degree of parallelism provided by the FPGA. The system reaches 350 and 270 VGA frames per second (fps) for the disparity and optical flow computations respectively in their mono-scale version and up to 32 fps for the multi-scale scheme extracting all the described features in parallel. In this work we also analyze the performance in accuracy and hardware resources of the proposed implementation.     

基于贪心算法和遗传算法的仓储车辆调度算法

针对仓储车辆调度问题提出一种基于贪心算法与遗传算法的调度算法。它主要利用遗传算法为框架筛选、进化出高效的调度方案,算法又融合了贪心算法对调度中的任务排序进行了快速优化。此融合使得遗传算法的编码简便,排除了不可行解的可能,从而使得算法性能大大提高。算法已经C++语言编程实现,实验分析证明:算法有效地提升了调度方案的效率。     

A model and software architecture for MMORPG traffic generation based on player behavior

In this paper we present a software architecture for traffic generation based on application level player behavior in Massively Multiplayer Online Role-Playing Games (MMORPGs). We have performed measurements of network traffic for each of the previously defined action categories for MMORPGs (Trading, Questing, Dungeons, Raiding, Player versus Player Combat, and Uncategorized), as well as measurements of application level player behavior in terms of listed action categories. Based on the obtained datasets we have created network traffic models for each action category and player behavior models with focus on hourly and daily trends. Network traffic models are implemented in Distributed Internet Traffic Generator and verified through comparison with the real traffic. Player behavior models explore number of active players, session duration, as well as lengths and probability of session segments (i.e., parts of the session consisting of only one category of player actions). We propose an architecture which enables scalable, behavior-driven traffic generation and implement it in a laboratory testbed. In order to achieve scalability of the system, we use Linux Containers as a virtualization technique. The resulting implementation can generate hundreds of MMORPG streams on a single PC. As a case study we used Activision Blizzard’s World of Warcraft.     

A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention

Pattern matching is one of the most performance-critical components for the content inspection based applications of network security, such as network intrusion detection and prevention. To keep up with the increasing speed network, this component needs to be accelerated by well designed custom coprocessor. This paper presents a parameterized multilevel pattern matching architecture (MPM) which is used on FPGAs. To achieve less chip area, the architecture is designed based on the idea of selected character decoding (SCD) and multilevel method which are analyzed in detail. This paper also proposes an MPM generator that can generate RTL-level codes of MPM by giving a pattern set and predefined parameters. With the generator, the efficient MPM architecture can be generated and embedded to a total hardware solution. The third contribution is a mathematical model and formula to estimate the chip area for each MPM before it is generated, which is useful for choosing the proper type of FPGAs. One example MPM architecture is implemented by giving 1785 patterns of Snort on Xilinx Virtex 2 Pro FPGA. The results show that this MPM can achieve 4.3 Gbps throughput with 5 stages of pipelines and 0.22 slices per character, about one half chip area of the most area-efficient architecture in literature. Other results are given to show that MPM is also efficient for general random pattern sets. The performance of MPM can be scalable near linearly, potential for more than 100 Gbps throughput. Supported by the National Natural Science Foundation of China (Grant No. 60803002), and the Excellent Young Scholars Research Fund of Beijing Institute of Technology     

Five-axis tool path generation for a flat-end tool based on iso-conic partitioning

Traditionally, for the flat-end tool, due to the intertwined dependence relationship between its axis and reference point, most 5-axis tool-path generation algorithms take a decoupled two-stage strategy: first, the so-called cutter contact (CC) curves are placed on the part surface; then, for each CC curve, tool orientations are decided that will accommodate local and/or global constraints such as minimum local gouging and global collision avoidance. For the former stage, usually simplistic “offset” methods are adopted to determine the cutter contact curves, such as the iso-parametric or iso-plane method; whereas for the latter, a common practice is to assign fixed tilt and yaw angle to the tool axis regardless the local curvature information and, in the case of considering global interference, the tool orientation is decided solely based on avoiding global collision but ignoring important local machining efficiency issues. This independence between the placement of CC curves and the determination of tool orientations, as well as the rigid way in which the tilt and yaw angle get assigned, incurs many undesired problems, such as the abrupt change of tool orientations, the reduced efficiency in machining, the reduced finishing surface quality, the unnecessary dynamic loading on the machine, etc. In this paper, we present a 5-axis tool-path generation algorithm that aims at alleviating these problems and thus improving the machining efficiency and accuracy. In our algorithm, the CC curves are contour lines on the part surface that satisfy the iso-conic property — the surface normal vectors on each CC curve fall on a right small circle on the Gaussian sphere, and the tool orientations associated to a CC curve are determined by the principle of minimum tilt (also sometimes called lead) angle that seeks fastest cutting rate without local gouging. Together with an elaborate scheme for determining the step-over distance between adjacent CC curves that seeks maximum material removal, the presented algorithm offers some plausible advantages over most existing 5-axis tool-path generation algorithms, particularly in terms of reducing the angular velocity and acceleration of the rotary axes of the machine. The simulation experiments of the proposed algorithm and their comparison with a leading commercial CAM software toolbox are also provided that demonstrate the claimed advantages.     

A program design language based software maintenance tool

Program design languages are an increasingly important method of expressing the detailed design of a software system. Such languages can be modelled using a data structure known as a semantic net. This paper describes a maintenance tool for program design languages based on such a data structure. The tool allows the user to interrogate a semantic net using an interactive procedural language in order to derive information necessary for software maintenance. The technique upon which this tool is based is applicable to the maintenance of activities throughout the software lifecycle.     

The design and implementation of a code generation tool

A practical approach to the development of a high-quality, re-usable code generator is described in this paper. This code generator produces code for the Prime 64V mode architecture, but the methodology used is generally applicable to the construction of compilers for most architectures. The code generator accepts a tree-structured intermediate form, linearized and represented as a file of integers. This intermediate form uses high-level operators, minimizing work by compiler front-ends that use it and providing a number of advantages in the code generation process. The output of the code generator is assembly language. This tool was found to considerably extend the capabilities of students in a graduate compiler class and has been used in the construction of Pascal and C compilers.     

Knowledge based quality-driven architecture design and evaluation

Modelling and evaluating quality properties of software is of high importance, especially when our every day life depends on the quality of services produced by systems and devices embedded into our surroundings. This paper contributes to the body of research in quality and model driven software engineering. It does so by introducing; (1) a quality aware software architecting approach and (2) a supporting tool chain. The novel approach with supporting tools enables the systematic development of high quality software by merging benefits of knowledge modelling and management, and model driven architecture design enhanced with domain-specific quality attributes. The whole design flow of software engineering is semi-automatic; specifying quality requirements, transforming quality requirements to architecture design, representing quality properties in architectural models, predicting quality fulfilment from architectural models, and finally, measuring quality aspects from implemented source code. The semi-automatic design flow is exemplified by the ongoing development of a secure middleware for peer-to-peer embedded systems.     

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.     

A parallel architecture for discrete relaxation algorithm

Discrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conventional hardware design for a Discrete Relaxation Algorithm (DRA) suffers from O(n2m3) time complexity and O(n2m2) space complexity. By reformulating DRA into a parallel computational tree and using a multiple tree-root pipelining scheme, time complexity is reduced to O(nm), while the space complexity is reduced by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm). Furthermore, a technique for dynamic configuring an architectural wavefront is used which leads to an O(n) time highly concurrent DRA3 architecture.     

A novel clock generation algorithm for system-on-chip based on least common multiple

Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.     

基于SDN架构的垂直切换算法

针对当前大部分垂直切换算法采用分布式局部寻优策略,容易导致网络拥塞的问题,提出一种基于软件定义网络(softwaredefinednetwork,SDN)架构的垂直切换算法。利用SDN获得全局网络状态信息,设计模糊逻辑控制模型对网络多属性参数进行归一化决策处理与收益计算,结合二阶马尔可夫模型预测未来全局网络的实际状态,实现异构无线网络的集中控制与切换决策。实验结果表明,所提算法在节点移动的动态性条件下能获得较优的切换性能,可以满足异构无线网络通信的切换需求。     

基于Min-Min改进后的网格调度算法

在对于网格计算中现有的任务调度算法的研究基础上，仔细分析了调度算法中最经典的Min-min算法，指出了该算法中所存在的负载不平衡的缺点，并在该算法的基础上提出了一个改进模型来有效的平衡负载，同时给出了相应的Balance-Min-Min算法。最后采用SimGrid工具包对所提出的算法进行仿真，验证了算法的合理性和高效性。     

Scheduling algorithm based on prefetching in MapReduce clusters

Due to cluster resource competition and task scheduling policy, some map tasks are assigned to nodes without input data, which causes significant data access delay. Data locality is becoming one of the most critical factors to affect performance of MapReduce clusters. As machines in MapReduce clusters have large memory capacities, which are often underutilized, in-memory prefetching input data is an effective way to improve data locality. However, it is still posing serious challenges to cluster designers on what and when to prefetch. To effectively use prefetching, we have built HPSO (High Performance Scheduling Optimizer), a prefetching service based task scheduler to improve data locality for MapReduce jobs. The basic idea is to predict the most appropriate nodes for future map tasks based on current pending tasks and then preload the needed data to memory without any delaying on launching new tasks. To this end, we have implemented HPSO in Hadoop-1.1.2. The experiment results have shown that the method can reduce the map tasks causing remote data delay, and improves the performance of Hadoop clusters.     

基于QoS的任务分类调度算法

分析了QoS Guided Min-Min及其改进算法,指出了这些算法调度不均衡的缺点.在此基础上设计出基于QoS的任务分类调度算法.先对特殊任务使用Min-Min方法进行调度,然后采用贪心策略对一般任务进行调度,转移或交换最大负载和最小负载机器上的一般任务,使各机器上的任务快速达到均衡.实验表明该算法在保证应用QoS的前提下,相对于以往算法负载分布更加均衡,任务总的完成时间更短.     

Linear rotation based algorithm and systolic architecture for solving linear system equations

A linear rotation based algorithm is proposed for solving linear system equations, Ax = b. This algorithm modified the conventional Gaussian elimination method and can avoid the problems of numerical singularity and ill condition. In this study, the implementation of a trapezoidal systolic array of n²/2 + n −2 processors as well as a linear array of n processors are accomplished for this algorithm. The trapezoidal systolic array performs the triangularization of a matrix A by using the modified linear rotation algorithm; while the linear array performs the backward substitution for evaluating the solution of x. The computing time for solving a linear equation system will be O(5n) time units. Also an implicit representation of the elimination factor by means of the sign parameter sequence instead of an numerical value is introduced for simplifying the hardware complexity. It is clear that this systolic architecture is simple, uniform, and regular, and therefore well suitable for the implementation of a VLSI chip.     

A random close packing based algorithm for the generation of continuous random networks

We present a generally applicable method for the modeling of covalent amorphous networks. The algorithm proceeds by generating random close packings of anions, followed by an optimal placement of the cations. As examples, we apply the algorithm to a-SiO₂, a-Si₃N₄, a-SiO_3/2N_1/3, and a-B₂O₃.     

A novel attribute-based generation architecture for facial image editing

Multimedia Tools and Applications - Facial image editing is one of the hot topics in recent years due to the great development in deep generative models. Current models are either based on...