Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.     

遥感影像的高性能并行处理技术研究

随着空间遥感技术和对地观测技术的不断发展,光学、热红外和微波等不同技术手段可以获取同一地区的多种遥感影像数据（多时相、多光谱、多传感器、多平台和多分辨率等）,每天获取的遥感数据量越来越大。同时,大量的遥感应用需要快速地对这些遥感数据进行处理与分析,提供辅助决策信息。因此,如果不能及时进行数据处理,这些数据就会失去时效性,甚至失去数据本身的价值。高性能计算与并行处理技术,加速了遥感影像数据处理与信息提取的进度,如大规模多处理系统、网格与云计算技术、通用图形处理器（GPGPU）等。文中综述了高性能计算、并行处理及云计算技术应用于遥感领域的最新进展,给出了一些研究与应用范例,并提出了当前高性能遥感影像处理所面临的一些挑战。     

FPGA implementation of collaborative representation algorithm for real-time hyperspectral target detection

Hyperspectral image contains various wavelength channels and the corresponding imagery processing requires a computation platform with high performance. Target and anomaly detection on hyperspectral image has been concerned because of its practicality in many real-time detection fields while wider applicability is limited by the computing condition and low processing speed. The field programmable gate arrays (FPGAs) offer the possibility of on-board hyperspectral data processing with high speed, low-power consumption, reconfigurability and radiation tolerance. In this paper, we develop a novel FPGA-based technique for efficient real-time target detection algorithm in hyperspectral images. The collaborative representation is an efficient target detection (CRD) algorithm in hyperspectral imagery, which is directly based on the concept that the target pixels can be approximately represented by its spectral signatures, while the other cannot. To achieve high processing speed on FPGAs platform, the CRD algorithm reduces the dimensionality of hyperspectral image first. The Sherman–Morrison formula is utilized to calculate the matrix inversion to reduce the complexity of overall CRD algorithm. The achieved results demonstrate that the proposed system may obtains shorter processing time of the CRD algorithm than that on 3.40 GHz CPU.     

Application design for configurable computing

Configurable computing systems enhance traditional computing systems through the addition of programmable hardware. Configurable computing offers the opportunity to change the partition at run-time by re-programming the hardware. Recent research has shifted to CAD and application development tools. Almost all existing configurable computing systems are based on field-programmable gate arrays (FPGAs). These devices implement reasonably arbitrary digital circuits, and the flexibility allows us to think of configurable computing systems based on FPGAs as netlist computers. The configurable computing approach integrates FPGAs as an intimate and fundamental component of the computing system, rather than relegating them to their earlier role of supporting system prototyping and low-volume production. However, the author believes that automated approaches to the design of configurable computing systems are premature because they do not pay enough attention to performance     

基于二维FFT的图像滤波方法及实现

二维快速傅立叶变换(FFT)在一个传统概念的处理机上实现时,需要芯片具有更多的逻辑资源。本文给出了基于FPGA的自定义处理机(CCM)的二维FFT算法和实现。在CCM的Splash-2平台上实现了二维FFT,计算速度达到180Mflops,最快速度超过Sparc-10工作站的23倍。同时,对于一个N×N图像,这种实现方法可以满足二维FFT所需要的O(N2log2N)次的浮点算术运算。     

Configurable processors for embedded computing

We have all heard about the increasing software content of embedded systems. To those who think of embedded software as autonomous programs hidden deep within the system, plugging away transparently and reliably on dedicated tasks, this increase might suggest that these programs are somehow becoming larger. In reality, the ongoing increases in processor performance let system designers implement in software what previously required dedicated or custom hardware blocks and accelerators. Indeed, given a choice, system designers might actually prefer the flexibility of implementing all embedded applications in software on programmable processors. However, parts of the applications must often run under critical time, performance, power, and cost constraints. Thus, designers have traditionally mapped these segments into custom hardware, such as application-specific integrated circuits (ASICs), or into reprogrammable fabrics, such as field programmable gate arrays (FPGAs). Ever-increasing chip capacities have given rise to configurable processors that offer virtually unlimited choices in core architectures.     

KAIST image computing system (KICS): A parallel architecture for real-time multimedia data processing

An efficient parallel architecture is proposed for high-performance multimedia data processing using multiple multimedia video processors (MVP; TMS320C80), which are fully programmable general digital signal processors (DSP). This paper describes several requirements for a multimedia data processing system and the system architecture of an image computing system called the KAIST Image Computing System (KICS). The performance of the KICS is evaluated in terms of its I/O bandwidth and the execution time for some image processing functions. An application of the KICS to the real-time Moving Picture Expert Group 2 (MPEG-2) encoder is introduced. The programmability and the high-speed data-access capability of the KICS are its most important features as a high-performance system for real-time multimedia data processing.     

SPINE: a domain‐specific framework for rapid prototyping of WBSN applications

Wireless body sensor networks (WBSNs) enable a broad range of applications for continuous and real‐time health monitoring and medical assistance. Programming WBSN applications is a complex task especially due to the limitation of resources of typical hardware platforms and to the lack of suitable software abstractions. In this paper, SPINE (signal processing in‐node environment), a domain‐specific framework for rapid prototyping of WBSN applications, which is lightweight and flexible enough to be easily customized to fit particular application‐specific needs, is presented. The architecture of SPINE has two main components: one implemented on the node coordinating the WBSN and one on the nodes with sensors. The former is based on a Java application, which allows to configure and manage the network and implements the classification functions that are too heavy to be implemented on the sensor nodes. The latter supports sensing, computing and data transmission operations through a set of libraries, protocols and utility functions that are currently implemented for TinyOS platforms. SPINE allows evaluating different architectural choices and deciding how to distribute signal processing and classification functions over the nodes of the network. Finally, this paper describes an activity monitoring application and presents the benefits of using the SPINE framework. Copyright © 2010 John Wiley & Sons, Ltd.     

基于MAP-CA的视频多点处理系统的研究与实现

文中介绍了一种高性能媒体信号处理器MAP-CA，它具备对视音频信号进行压缩处理的优化结构和多种方便的标准音视频接口。针对视频会议中视频信息的处理需求，以MAP—CA为核心处理器，设计了一个基于PC机的插卡式视频多点处理子系统，可应用于视频会议中多路码流的实时合成和转换，并且不会增加PC机负担。     

A cross-platform test tool for digital image processing

Image processing is one of the current research topics widely used in different engineering fields. Therefore, it is taught as a lesson under different names in various engineering departments. In-class applications are usually done through programs that depend on desktop platforms such as Windows, Linux or MacOS. These platforms, which self or its camera are fixed, can only take real time images with limited mobility. It is difficult to apply image processing algorithms for real time images and make comparisons. In this study, a cross-platform test tool for image processing was developed. This tool can work on desktop platforms such as Windows and MacOS, as well as mobile platforms such as Android and IOS. Thanks to mobile platform support, the real time images can be taken anytime and anywhere. The basic image processing operations can be performed on recorded or real time images. The resulting images can be recorded. Thus, a test environment is provided to apply and compare different methods and algorithms.

     

Service-oriented grid computing system for digital rights management (GC-DRM)

Service-oriented computing and applications have recently gained significant attention since they provide new service infrastructure and development of service-oriented technology. Under such trend and ubiquitous computing requirement, grid computing is becoming popular in scientific and enterprise computing due to its flexible deployment and implementation. In this paper, we proposed a service-oriented digital rights management (DRM) platform based on grid computing (called GC-DRM) which is in the compliance of Grid Portal standards by using porlet. The platform integrates Globus Toolkit 4 and Condor 6.9.2 and uses web 2.0 to construct the web-based user interface for providing job submission, control, management, monitor for DRM services. GC-DRM can provide different categories of services which include watermark embedding and extraction, image scrambling, visible watermark embedding, image tamper-detection and recovery. In addition, GC-DRM has been applied to analyze the robustness of digital watermark by filter bank selection and the performance can be improved in the aspect of speedup, stability and processing time compared with NaradaBrokering based Computing Power Services (NB-CPS) and Web Services based Computing Power Service (WS-CPS). Therefore, GC-DRM can be concluded as a superior service-oriented computing which provides the user friendly environment with efficient DRM service performance based on grid computing architecture.     

The density advantage of configurable computing

More and more, field-programmable gate arrays (FPGAs) are accelerating computing applications. The absolute performance achieved by these configurable machines has been impressive-often one to two orders of magnitude greater than processor-based alternatives. Configurable computing is one of the fastest, most economical ways to solve problems such as RSA (Rivest-Shamir-Adelman) decryption, DNA sequence matching, signal processing, emulation, and cryptographic attacks. But questions remain as to why FPGAs have been so much more successful than their microprocessor and DSP counterparts. Do FPGA architectures have inherent advantages? Or are these examples just flukes of technology and market pricing? Will advantages increase, decrease, or remain the same as technology advances? Is there some generalization that accounts for the advantages in these cases? The author attempts to answer these questions and to see how configurable computing fits into the arsenal of structures used to build general, programmable computing platforms     

On-chip template training system and image processing applications using iterative annealing on ACE16k chip

Cellular neural networks proved to be a useful parallel computing system for image processing applications. Cellular neural networks (CNNs) constitute a class of recurrent and locally coupled arrays of identical cells. The connectivity among the cells is determined by a set of parameters called templates. CNN templates are the key parameters to perform a desired task. One of the challenging problems in designing templates is to find the optimal template that functions appropriately for the solution of the intended problem. In this paper, we have implemented the Iterative Annealing Optimization Method on the analog CNN chip to find an optimum template by training a randomly selected initial template. We have been able to show that the proposed system is efficient to find the suitable template for some specific image processing applications.     

BOAR: an advanced HW/SW coemulation environment for DSP system development

The BOAR emulation system is targeted to hardware/software (HW/SW) codevelopment of advanced embedded DSP and telecom systems. The challenge of the BOAR system is efficient customization of programmable hardware, and dedicated partitioning routine to target applications and structures, which allows quite high overall system performance. The system allows multiple configurations for communication between processors and field programmable gate arrays (FPGAs) making the BOAR system an efficient tool for real-time HW/SW coverification. The reprogrammable hardware of the emulation tool is based on four Xilinx 4000-series devices, two Texas TMS320C50 signal processors and one Motorola MC68302 microcontroller. With current devices the BOAR hardware provides approximately 40–70 kgates of logic capacity in DSP applications. The emulation capacity can be expanded by connecting several similar boards in chain. The system has also a versatile internal reprogrammable test environment for test bench development, performance evaluations and design debugging. The logic development environment is based on the Synopsys synthesis tools and an automatic design management software, which performs resource mapping and performance-driven design partitioning between FPGAs. The emulation hardware is currently connected to logic and software development environments via an RS-232C bus. The BOAR emulation system has been found a very efficient platform for real-life prototyping of different types of DSP algorithms and systems, and validating correct functionality of a VHDL macro library.     

面向边缘智能计算的异构并行计算平台综述

边缘智能计算对硬件资源的需求复杂多元,传统计算平台难以为继,异构并行计算平台成为边缘智能算法落地的关键途径之一。以深度学习算法和边缘计算为牵引,对异构并行计算平台展开研究。一方面,阐述了传统计算平台适配实现边缘智能计算的优缺点,指出边缘端应用场景中传统计算平台算力与功耗矛盾突出等局限性,并以指令模型、通讯机制和存储体系三个关键技术为线索梳理技术发展脉络。另一方面,从运算速度、功耗等角度重点对比分析了近年来典型异构平台较新的代表性产品,然后针对不同应用场景和约束条件给出了异构平台的选择建议：优先选择CPU+X组合的异构平台。功耗要求严格约束下的应用建议优先选择CPU+FPGA组合;功能迭代更新快的场景建议优先选择CPU+GPU组合;算法成熟且对实时性和功耗均具有高要求的应用优先选择ASIC计算平台。提出了异构并行计算平台在指令模型统一、通讯机制轻量化、存储体系灵活性以及开发生态完备化四个方面的问题与挑战,期望能为该领域研究人员带来一定的启发。     

Computational architectures for sonar array processing in autonomous rovers

This paper presents design of novel embedded computational architectures for real time, in-motion mapping based on ultrasound sensors for use in resource constrained autonomous rovers. Autonomous rovers are a class of real time systems that are constrained for size, weight, on-board computational resources and power. Embedded computing architectures designed for implementing the mapping and navigational algorithms must optimize the use of these resources. In the process of map generation, raw sensor data obtained from an array of ultrasound sensors is filtered for sensor noise using probabilistic sensor model, and probabilistic data fusion methods are employed for spatial and temporal correlation of data for improving the map. In this paper, we present a System-on-Chip design based design space exploration of embedded computational architectures for implementation on field programmable gate arrays. We seek to exploit system level, region level and sensor level parallelism in the mapping algorithm for enhancing the throughput. Design space exploration is carried out by employing existing soft core processors, designing custom co-processors and data path modules and integrating them using parallel and pipelined data flow approaches. Results of mapping a test area on all the architectures are compared to characterize the performance and suitability of the proposed architectures.     

A Java-based parallel platform for the implementation of evolutionary computation for engineering applications

As computers continually improve in performance and decrease in manufacturing cost, distributed systems consisting of multiple computers implemented as parallel computation platforms have become viable for engineering applications which demand intensive computation power. This paper proposes an extended version of a previously developed low cost parallel computation platform called para worker. The system is based on a cluster structure which is a form of a distributed system. The new system is termed para worker 2 which differentiates it from the earlier system. The new proposed system adds enhanced features of improved dynamic object reallocation, adaptive consistency protocols, and location transparency. Performance of the para worker 2 has proven to be superior to the para worker. Testing was based on an execution of Genetic Algorithm to solve the Economic Dispatch problem in Power Engineering. The proposal is particularly useful for the implementation and execution of computational intelligence techniques such as evolutionary computing for engineering applications.     

A real-time near infrared image acquisition system based on image quality assessment

This paper presents a real-time image acquisition system with an improved image quality assessment module to acquire high-quality near infrared (NIR) images. Thermal imaging plays a vital role in a wide range of medical and military applications. The demand for high-throughput image acquisition and image processing has continuously increased especially for critical medical and military purposes where executions under real-time constraints are required. This work implements an NIR image quality assessment module, which utilizes improved two-dimensional entropy and mask-based edge detection algorithms. The effectiveness of the proposed image quality assessment algorithms is demonstrated through the implementation of a complete finger-vein biometric system. The proposed model is implemented as an embedded system on a field programmable gate array prototyping platform. By including the image quality assessment module, the proposed system is able to achieve a recognition accuracy of 0.87 % equal error rate, and can handle real-time processing at 15 frames/s (live video rate). This is achieved through hardware acceleration of the proposed image quality assessment algorithms via a novel streaming architecture.     

基于CORBA的分布式信息交换处理系统模型

讨论了分布对象技术在大型分布式企业计算环境中的应用,给出了分布式信息交换处理系统的软件体系结构和模型实现。传统的大型分布式企业计算环境具有如下应用特征：异构平台繁多、存在多种遗留应用、大量业务应用系统不能实现透明的互联互操作。针对上述特征,系统采用当前分布对象技术中的主流－CORBA技术,设计与实现了一个分布式信息交换处理集成平台,为企业内部繁多的业务应用系统提供了一个应用集成框架,将企业内各类复杂的计算资源集成为一个有机的整体。     

A hardware-software codesign methodology for DSP applications

The authors describe a systematic, heterogeneous design methodology using the Ptolemy framework for simulation, prototyping, and software synthesis of systems containing a mixture of hardware and software components. They focus on signal-processing systems in which the hardware typically consists of custom data paths, finite-state machines (FSMs), glue logic and programmable processors. The software is one or more embedded programs running on the programmable components