A networks-on-chip architecture design space exploration – The LIB

Many on-chip network circuit and architecture techniques are incompatible with modern design flows, making them unsuitable for use in systems-on-chip. This paper presents a networks-on-chip (NoC) architecture design space exploration method for multi-processor systems-on-chip architecture. The NoC architecture design space is designed with a Layer-Interactive-Building block (LIB) methodology that is divided into three layers: application layer, link/network layer, and physical layer. The suggested LIB design paradigmatic philosophy provides modular building block structure in both hardware and software and the protocols for their interconnection in the three architecture layers. Using LIB the designer can easily select these building blocks to build application-specific NoCs to meet different application requirements such as media, graphic, software radio and communication network applications. The LIB provides the NoC building blocks, architecture interacting systems-on-chip components, the programming models and application mapping strategies. The LIB can be used as a complementary library and tools for future on-chip interconnection network design.     

Exascale design space exploration and co-design

The co-design of architectures and algorithms has been postulated as a strategy for achieving Exascale computing in this decade. Exascale design space exploration is prohibitively expensive, at least partially due to the size and complexity of scientific applications of interest. Application codes can contain millions of lines and involve many libraries. Mini-applications, which attempt to capture some key performance issues, can potentially reduce the order of the exploration by a factor of a thousand. However, we need to carefully understand how representative mini-applications are of the full application code. This paper describes a methodology for this comparison and applies it to a particularly challenging mini-application. A multi-faceted methodology for design space exploration is also described that includes measurements on advanced architecture testbeds, experiments that use supercomputers and system software to emulate future hardware, and hardware/software co-simulation tools to predict the behavior of applications on hardware that does not yet exist.     

Qualitative design support for engineering and architecture

Conventional design support software tools cannot effectively manage the complex, heterogeneous information used in engineering and architecture (EA) tasks. Crucially, despite uncertainty being an inherent quality of EA information particularly in the early stages of a design project, current tools solely rely on numerical approaches which do not support such incomplete and vague information. In this paper, we establish a complete framework for developing qualitative support tools that directly address these shortcomings. Our framework is application oriented and addresses the broader issues surrounding the actual use of qualitative methods. It provides design principles and strategies that allow a software engineer to develop custom qualitative software tools according to their specific EA task specifications. Our framework also provides the engineer with practical theory and guidelines for implementing their custom qualitative model and validating their system using context specific test data. We demonstrate the validity of our framework by presenting a case study in architectural lighting in which a prototype qualitative reasoning engine successfully automates qualitative logic about the subjective impressions of a lighting installation.     

STATS: A framework for microprocessor and system-level design space exploration

As microprocessor-based systems grow in complexity, and the processor-memory speed gap widens further, more emphasis needs to be placed on early design space exploration in order to produce the highest performance systems with minimal schedule impact. We discuss the critical issues associated with architectural evaluation of complex microprocessor-based systems, and present a methodology for the comprehensive and semiautomatic evaluation of processor, cache hierarchy, system interconnect, and main memory architectural and technological alternatives. We discuss the implementation of the methodology, and describe how it can be used in early design space exploration. The unique aspects of the methodology are further illustrated through two architectural investigations performed using the toolset.     

Using design space exploration for finding schedules with guaranteed reaction times of synchronous programs on multi-core architecture

The synchronous model of computation is well suited for real-time systems, because it allows static analysis in order to find and guarantee their reaction times. Today’s multi-core systems are becoming the predominant computing platforms. Synchronous programs are typically compiled into single threaded code, which makes them unsuitable for exploiting parallelism of the multi-core platforms. Moreover, static timing analysis becomes highly intractable for multi-core systems. This article proposes a novel methodology that aims at finding the mapping and schedule of synchronous programs that guarantees, statically, reaction times when mapped onto a multi-core system consisting of two types of time-predictable cores. The proposed methodology combines design space exploration based on evolutionary algorithm and scheduling of parts of synchronous programs. It allows minimizing the resource usage in terms of number of cores by finding the mapping and schedule with the guaranteed reaction time for architectures with different number of cores. In particular, we: (a) transform a synchronous program written in synchronous SystemJ to a graph-based model represented with two types of computation nodes suitable for execution on two types of time-predictable cores, (b) perform mapping of computation nodes on a customizable multi-core platform using genetic operations, and (c) generate a resulting static schedule of computation nodes for each mapping as part of the design space exploration. The design flow, from program specification and node mapping to the design space exploration and multi-core scheduling is completely automated.     

通用处理器和图像处理器新型融合架构分析

CPU与图形处理器(GPU)作为两种主要的通用处理器,在协同工作时存在功耗过大、体积不易压缩、传输速度慢等问题,因而融合成为一种趋势。在分析两者技术特点及通过高性能基准程序实测其性能基础上,提出一种新型融合架构。该融合架构采用低功耗处理器进行任务分配,根据任务类型及计算量,平衡串行处理核心和并行处理核心之间的任务调度及使用效率;而两种处理核心专注于进行数据处理,根据不同任务采用不同组合方式。通过性能评估,该新融合架构在计算能力和功耗方面均有较大改善。     

Chip size estimation for SOC design space exploration

At early design space exploration phases of architectures for Systems On a Chip (SOC) chip size estimation is of high interest. An accurate chip size estimation needs detailed knowledge of the transistor densities of a semiconductor process. This paper introduces a novel and simplified chip size estimator, which is independent of manufacturer specific process data. CMOS processes are characterized by only three parameters. These are the drawn gate length and the used numbers of metal layers for logic and for memories. The chip size estimator has been derived from a comprehensive analysis of realized VLSI chips. It has been investigated and confirmed either for published VLSIs as well as for latest SOC designs with 221 million transistors and 333 million transistors. The proposed model has been implemented as a web based tool and contributes to analytical modeling of cost and performance tradeoffs of SOC concepts.     

Efficient design space exploration for application specific systems-on-a-chip

A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip (SoC) platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a SoC platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration (DSE) in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy Systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized SoC platform based on a parameterized VLIW processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established DSE approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time.     

Interdigitation for effective design space exploration using iSIGHT

Optimization studies for nonlinear constrained problems (i.e. most complex engineering design problems) have repeatedly shown that (i) no single optimization technique performs best for all design problems, and (ii) in most cases, a mix of techniques perform better than a single technique for a given design problem. iSIGHT^TM is a generic software framework for integration, automation, and optimization of design processes that has been developed on the foundation of interdigitation: the strategy of combining multiple optimization algorithms to exploit their desirable aspects for solving complex problems. With the recent paradigm shift from traditional optimization to design space exploration for evaluating “what-if” scenarios and trade-off studies, iSIGHT has grown from an optimization software system to a complete design exploration environment, providing a suite of design exploration tools including a collection of optimization techniques, design of experiments techniques, approximation methods, and probabilistic quality engineering methods. Likewise, the interdigitation design methodology embodied in iSIGHT has grown to support the interdigitation of all design exploration tools for effective design space exploration. In this paper we present an overview of iSIGHT, past and present, of the interdigitation design methodology and its implementation for multiple design exploration tools, and of an industrial case study for which elements of this methodology have been applied. Received December 30, 2000     

Employing early model-based safety evaluation to iteratively derive E/E architecture design

ISO 26262 addresses development of safe in-vehicle functions by specifying methods potentially used in the design and development lifecycle. It does not indicate what is sufficient and leaves room for interpretation. Yet the architects of electric/electronic systems need design boundaries to make decisions during architecture evolutionary design without adding a risk of late changes. Correct selection of safety mechanisms from alternatives at early design stages is vital for time-to-market of critical systems. In this paper we present and discuss an iterative architecture design and refinement process that is centered around ISO 26262 requirements and model-based analysis of safety-related metrics. This process simplifies identification of the most sensitive parts of the architecture, selection of the best suitable safety mechanisms to reduce thereby failure rate on the system level and improve the metrics defined by the standard. To support the defined process we present the metamodels that can be integrated with existing DSL (domain-specific language) frameworks to extend them with information supporting further extraction of fault propagation behavior. We provide a framework for architecture model analysis and selection of safety mechanisms. We provide details on the model-based toolset that has been developed to support the proposed analysis and synthesis methods, and demonstrate its application to analysis of a steer-by-wire system model and selection of safety mechanisms for it.     

Gamifying model-based engineering: the PapyGame experience

Software and Systems Modeling - Modeling is an essential and challenging activity in any engineering environment. It implies some hard-to-train skills such as abstraction and communication....     

A new software architecture for developing and testing algorithms for space exploration missions

In recent years, planet exploration has received an increasing interest due to the possibility of exploiting planet resources and assuring a human–robotic colonized presence on suitable planetary surfaces. These goals can be reached through the development of smart robots, which are able to work on their own and without requiring a constant human supervision but, at the same time, assuring a great level of safety and reliability. To this aim, the development of effective architectures, concerning both software and hardware issues, could represent a great improvement toward this ambitious objective. This paper presents a novel modular architecture called Test Bench for Robotics and Autonomy (TBRA), the main objective of which is to create a test bench for rover autonomy missions where different implementations of a particular subsystem can be easily tested, while keeping the rest of the system unchanged. Thus, it allows the developers to be able to compare the results of tests and understand which version works better. Such architecture has been built on top of the Workframe, a generic middleware for real-time robotics. This two-layered approach allows the final user to deal only with the TBRA interface, which is designed to be extremely simple to use and takes care of most real-time programming problems, while allowing flexibility in the development, maintenance and future extension of the TBRA itself.     

Applying Kansei engineering to industrial machinery trade show booth design

Trade shows are considered an important marketing channel for companies since they provide manufacturers and purchasers with a vital commercial platform. Traditionally, plastics and rubber industry trade shows have been ineffective due to poor booth planning. Nevertheless, few studies have examined trade show booth design and planning. Actually, most companies lack distinct goals, and their decisions regarding trade show participation may influence decisions regarding which products should be demonstrated, size of trade booth, and level of advertising. Such a decision-making is a problem involving multi-criteria decisions, and requires a logical and objective operating procedure. This work thus devises an objective procedure for trade show. This investigation focuses on booth design for plastics and rubber industry trade shows and comprises three parts: (1) selecting appropriate assessment criteria for trade show design using the Delphi method and Kansei engineering. (2) Establishing suitable booth design principles and procedures for plastics and rubber industry trade show using fuzzy product positioning. (3) Further employing the proposed method to design trade show booths and verify their performance. The results demonstrate the feasibility of the proposed method.

Relevance to industry

This study was conducted to support machinery vendors as a systematic design flow chart and related criteria to provide an objective approach to trade show booth planning.     

PASES: An energy-aware design space exploration framework for wireless sensor networks

Energy consumption is one of the most constraining requirements for the development and implementation of wireless sensor networks. Many design aspects affect energy consumption, ranging from the hardware components, operations of the sensors, the communication protocols, the application algorithms, and the application duty cycle. A full design space exploration solution is therefore required to estimate the contribution to energy consumption of all of these factors, and significantly decrease the effort and time spent to choose the right architecture that fits best to a particular application. In this paper we present a flexible and extensible simulation and design space exploration framework called “PASES” for accurate power consumption analysis of wireless sensor networks. PASES performs both performance and energy analysis, including the application, the communication and the platform layers, providing an extensible and customizable environment. The framework assists the designers in the selection of an optimal hardware solution and software implementation for the specific project of interest ranging from standalone to large scale networked systems. Experimental and simulation results demonstrate the framework accuracy and utility.     

Model-driven design space exploration for multi-robot systems in simulation

Multi-robot systems are increasingly deployed to provide services and accomplish missions whose complexity or cost is too high for a single robot to achieve on its own. Although multi-robot systems offer increased reliability via redundancy and enable the execution of more challenging missions, engineering these systems is very complex. This complexity affects not only the architecture modelling of the robotic team but also the modelling and analysis of the collaborative intelligence enabling the team to complete its mission. Existing approaches for the development of multi-robot applications do not provide a systematic mechanism for capturing these aspects and assessing the robustness of multi-robot systems. We address this gap by introducing ATLAS, a novel model-driven approach supporting the systematic design space exploration and robustness analysis of multi-robot systems in simulation. The ATLAS domain-specific language enables modelling the architecture of the robotic team and its mission and facilitates the specification of the team’s intelligence. We evaluate ATLAS and demonstrate its effectiveness in three simulated case studies: a healthcare Turtlebot-based mission and two unmanned underwater vehicle missions developed using the Gazebo/ROS and MOOS-IvP robotic platforms, respectively.