基于I-V特性的阻变存储器的阻变机制研究

随着器件尺寸的缩小,阻变存储器(RRAM)具有取代现有主流Flash存储器成为下一代新型存储器的潜力。但对RRAM器件电阻转变机制的研究在认识上依然存在很大的分歧,直接制约了RRAM的研发与应用。通过介绍阻变存储器的基本工作原理、不同的阻变机制以及基于阻变存储器所表现出的不同I-V特性,研究了器件的阻变特性;详细分析了阻变存储器的五种阻变物理机制,即导电细丝(filament)、空间电荷限制电流效应(SCLC)、缺陷能级的电荷俘获和释放、肖特基发射效应(Schottky emission)以及普尔-法兰克效应(Pool-Frenkel);同时,对RRAM器件的研究发展趋势以及面临的挑战进行了展望。     

阻变存储器及其集成技术研究进展

在各种新型非挥发性存储器中,阻变存储器(RRAM)具有成为下一代存储器的潜力.介绍了RRAM器件的基本结构,分类总结了常用的材料以及制备工艺,对RRAM阵列的集成方案进行了比较,并讨论了目前存在的问题;最后,对RRAM的研究趋势进行了展望.     

阻变存储器外围电路关键技术研究进展

阻变存储器(RRAM)是一种前景非常好的未来通用存储技术,也是当前国际学术界和工业界研究的热点。主要介绍了存储器外围电路的电路设计,并介绍了阻性存储器外围电路,包括验证电路、写电路、参考模块方案和形式、限流等关键技术的原理,重点讨论了提升复位操作速度,改善高阻值离散性,参考方案的设计和参考单元的组成,用限流实现低功耗操作的方法及其发展趋势。     

一种基于阻变单元特性的阻变存储器修复方案

针对新型阻变存储器(RRAM)工艺良率不高的问题,提出了一种新型的修复解决方案,该方案基于阻变单元的特殊性能,即初始状态为高阻,经过单元初始化操作过程后转变为低阻。利用这样特性的阻变单元作为错误检测位、冗余单元作为修复位,提出了三种不同的组织结构来实现修复操作。三种结构由于主存储器、检验位存储器及冗余存储器的组织方式不同,达到了不同的冗余存储器利用率。最后,通过数学分析可以证明,该方案在利用了较少冗余存储器的条件下,可以将阻变存储器的错误率普遍降低10～30倍,实现了较好的修复效果。     

铅基卤素钙钛矿阻变式存储器研究进展

随着数字通信在大数据以及物联网等领域的应用,推动了下一代存储设备的发展.阻变式存储器因其功耗低、尺寸可调、操作速度快等优点被认为是最有前景的信息存储器件之一.近年来,兼具成本低、带隙可调、载流子扩散长度长、离子迁移速率快、载流子迁移率高等优点的铅基卤素钙钛矿,在阻变式存储器领域引起了广泛关注.主要对铅基卤素钙钛矿阻变式...     

基于氧化钨的8 Mb高密度阻变存储器设计

设计了一款基于氧化钨的8Mb高密度阻变存储器,采用单晶体管开关、单电阻(1T1R)的存储器单元结构,设计了完整的存储单元、行列译码器、写驱动和灵敏放大器等关键模块。存储器芯片采用HHNEC 0.13μm 1P8M CMOS工艺流片。仿真结果表明,在8F2的高密度存储单元面积下,该存储器可实现准确的数据写入和读出功能。     

新型阻变存储器内的电压解决方案

相对于现在流行的FLASH型存储器,新型阻变存储器(resistive-RAM,RRAM)有很多优势,比如较高的存储密度和较快的读写速度。而针对RRAM的读写操作特性,提出了一种适用于新型阻变存储器的提供操作电压的电路。该方案解决了新型存储器需要外部提供高于电源电压的操作电压的问题,使得阻变存储器能应用于嵌入式设备。同时,对工艺波动和温度波动进行补偿,从而降低了阻变存储器的读写操作在较差的工艺和温度环境下的失败概率,具有很强的实际应用意义。该设计采用0.13μm标准CMOS 6层金属工艺在中芯国际(SMIC)流片实现,测试结果表明,采用此电路的RRAM能正确地进行数据编程和擦除等操作,测试结果达到设计要求。     

三维阻变存储器的研究进展

在我国信息产业高速发展的今天,传统存储器难以满足目前的数据存储需求,亟需发展新一代高性能存储器。阻变存储器(RRAM)因其具有结构简单、功耗低、集成密度高、读/写速度快等优势,被认为是最具发展潜力的新兴存储器之一。综述了三维RRAM的发展现状,分析了现阶段三维RRAM面临的漏电流、热串扰、均一性、可靠性等问题,重点探讨了针对以上问题的解决方案,并对于RRAM未来的应用前景进行了分析和预测,认为其在替代传统存储器、神经网络计算、芯片加密防护等方面有重要的应用前景。     

两类阻变机理及性能改善方法的研究

在新型非易失性存储领域,结构简单、高速低耗的阻变存储器具有巨大优势和很强的竞争力.简要介绍了阻变存储器的结构及其两个电阻转变行为.总结了两类阻变机理,探讨了阻变存储器性能优化的方法,以及优化方法在阻变性能与器件的可靠性和稳定性之间如何取得平衡统一的问题,并展望了其前景.     

一种提高阻变存储器擦除可靠性的写电路设计

针对现有阻变存储器中严重影响擦除操作可靠性的"写回"现象,结合测试数据、材料特性及电路原理分析了引起这种现象的主要原因,给出了一种加入"擦除反馈"功能的写电路设计方案。该方案能够对擦除操作进行监控,一旦发现操作完成,立即使用反馈电路关闭写驱动的输出以停止擦除操作,防止"写回"现象。优化后的写电路方案在0.13μm标准CMOS工艺下进行了流片验证。通过测试数据的分析对比,可以看到相比传统的写电路方案,采用文中的电路设计能明显降低"写回失效"的可能,大幅度提高擦除操作的可靠性。     

Configurable Resistive Switching between Memory and Threshold Characteristics for Protein‐Based Devices

The employ of natural biomaterials as the basic building blocks of electronic devices is of growing interest for biocompatible and green electronics. Here, resistive switching (RS) devices based on naturally silk protein with configurable functionality are demonstrated. The RS type of the devices can be effectively and exactly controlled by controlling the compliance current in the set process. Memory RS can be triggered by a higher compliance current, while threshold RS can be triggered by a lower compliance current. Furthermore, two types of memory devices, working in random access and WORM modes, can be achieved with the RS effect. The results suggest that silk protein possesses the potential for sustainable electronics and data storage. In addition, this finding would provide important guidelines for the performance optimization of biomaterials based memory devices and the study of the underlying mechanism behind the RS effect arising from biomaterials.     

HfO_x薄膜阻变特性及机理研究

采用射频磁控溅射法在Pt/Ti/SiO2/Si衬底上制备了Ta/HfOx/Pt三明治结构,对其电学性能和化学成分进行了分析。结果表明,Ta/HfOx/Pt结构具有明显的双极电阻转变特性,高低阻比(ROFF/RON)约26,并且具有良好的重复性与保持性,循环次数超过了200次。通过XPS和R-T数据分析证实,电场作用下HfOx层中因氧的逸出以及铪的富集所形成的铪导电细丝的生长、断裂和再生是该器件发生电阻转变的主要机制。     

Bipolar Resistive Electrical Switching of CuTCNQ Memories Incorporating a Dedicated Switching Layer

In this letter, we investigate bipolar resistive switching of CuTCNQ-based memory cells in which various types of oxides are incorporated as dedicated switching layer (SL) in a bottom $ hbox{electrode}!setminus!hbox{oxide}!setminus!hbox{CuTCNQ}!setminus!hbox{top electrode}$ configuration. The bottom electrode was Pt as well as $hbox{n}^{+}hbox{Si}$ . As oxide SL, we used $hbox{Al}_{2}hbox{O}_{3}$ , $hbox{HfO}_{2}$, $ hbox{ZrO}_{2}$, and $hbox{SiO}_{2}$. Au was employed as the top electrode. The basic memory characteristics appear to be independent of the type of oxide used. This gives clear indication that the materials investigated as SL mainly act as matrix in which conductive channels are formed and dissolved.      

Resistive Switching Characteristics of Sol–Gel Zinc Oxide Films for Flexible Memory Applications

Unipolar resistive switching devices are investigated for nonvolatile memory applications in a metal-insulator-metal structure in which the insulator layer is based on sol–gel-derived zinc oxide (ZnO) films prepared by a simple spin-coating process followed by thermal annealing. Fast programming ( $leq$ 50 ns) and a high off-to-on resistance ratio $(geq hbox{10}^{4})$ is demonstrated. The influences on the switching behaviors according to the crystallinity of the ZnO films are studied as a function of the annealing temperature. In addition, the devices are fabricated on a flexible plastic substrate and exhibit excellent durability upon repeated bending tests, demonstrating their potential for flexible low-cost memory devices.      

还原时间对AlOx/WOx RRAM开关速度的调制作用

基于128 kbit AlOx/WOx双层结构阻变存储器(RRAM)芯片,提出并验证了还原时间对RRAM开关速度的调制作用,同时设计了一种固定电压幅值逐步增大脉宽的算法用于RRAM阵列中速度的测试.还原处理的时间越长,AlOx层的厚度越薄,同时氧空位的含量增多,可加快导电细丝的形成、断裂和重新连接,进而提升芯片的开关速度.测试结果表明,还原时间由10 min增加至30 min,在4V和4.5V操作电压下,FORMING速度分布的均值分别由200 ns减小至120 ns和由100 ns减小至60 ns;在4V和4.5V操作电压下,RESET速度分布的均值分别由160 ns减小至120 ns和由120 ns减小至100 ns;SET速度分布的均值在4V电压下可由120 ns减小至80 ns.此外,还原时间的增长可以改善速度分布的一致性,减小速度的波动.     

Microstructure and Superconductivity of La1.85Sr0.15CuO4 Nanowire Arrays

Superconducting La_1.85Sr_0.15CuO₄ nanowire arrays are successfully synthesized through a sol–gel method combined with porous alumina as a morphology‐directing hard template for the first time. The morphology, structure, and composition of the as‐prepared nanowire arrays are characterized by field‐emission scanning electron microscopy, transmission electron microscopy, high‐resolution transmission electron microscopy, X‐ray diffraction, and energy‐dispersive X‐ray spectroscopy. These experimental results indicate that the nanowires are well crystallized with an approximately uniform diameter of about 30 nm. The superconducting transition temperature T_c (ca. 30 K) of the annealed nanowires is lower than that in bulk La_1.85Sr_0.15CuO₄. It is suggested that this superconductivity suppression is derived from the weakening of in‐plane hybridization in the nanowire system.     

Evolution of Electron Transport under Resistive Switching in Porphyrazine Films

Semiconductors - An analysis of the I–V characteristics makes it possible to determine the mechanisms of conduction corresponding to different states of the flow channels upon resistive...     

Scaling Behavior of Resistive Switching in Epitaxial Bismuth Ferrite Heterostructures

Resistive switching (RS) of (001) epitaxial multiferroic BiFeO₃/La_0.67Sr_0.33MnO₃/SrTiO₃ heterostructures is investigated for varying lengths scales in both the thickness and lateral directions. Macroscale current–voltage analyses in conjunction with local conduction atomic force microscopy (CAFM) reveal that whilst both the local and global resistive states are strongly driven by polarization direction, the type of conduction mechanism is different for each distinct thickness regime. Electrode‐area dependent studies confirm the RS is dominated by an interface mechanism and not by filamentary formation. Furthermore, CAFM maps allow deconvolution of the roles played by domains and domain walls during the RS process. It is shown that the net polarization direction, and not domain walls, controls the conduction process. An interface mechanism based on barrier height and width alteration due to polarization reversal is proposed, and the role of electronic reconstruction at the interface is further investigated.