A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13-/spl mu/m CMOS

A highly integrated 2-GHz, 0.13-/spl mu/m CMOS direct-conversion transmitter for wide-band code division multiple access (WCDMA) is described. Different circuit and calibration techniques are presented that successfully suppress the carrier leakage and enable the direct-upconversion architecture to meet all WCDMA specifications. The transmitter delivers +2.5 dBm output power while consuming only 45 mA from its nominal 1.5-V supply. The overall gain can be programmed in 1-dB steps over a 100-dB range with 0.4 dB accuracy. The transmitter achieves an OIP3 of +19.3 dBm, an error vector magnitude of 4.3%, and an adjacent channel leakage ratio of -38 dBc. The measured output noise of -146 dBm/Hz in the DCS Rx band and -149 dBm/Hz in the UMTS Rx band is sufficiently low to provide an option to increase the integration level even further by eliminating the external Tx interstage filter between the power amplifier and its driver.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS

In direct digital synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current: 11.5 mA).     

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS

A compact ultra-broadband MMIC-compatible uniplanar balun has been developed using offset air-gap coupler. The offset air-gap coupler presents tight coupling and low conductor loss, and thus allows the balun to show low loss at mm-wave frequencies. The measured insertion loss was less than 2 dB from 26 to 55 GHz, and amplitude and phase imbalance was less than /spl plusmn/1dB and 5/spl deg/, respectively over a wide frequency range from 27 to 69 GHz.     

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS

We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost, and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC, in a GPS receiver. The GPS chip, with a total size of 6.3 mm /spl times/ 6.3 mm, contains a 2.3 mm /spl times/ 2.0 mm radio part, including RF front end, phase-locked loops, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM, and dual port SRAM . It is fabricated using 0.18-/spl mu/m CMOS technology with a MIM capacitor and operates from a 1.6-2.0-V power supply. Experimental results show a very low power consumption of, typically, 57 mW for a fully functional chip including baseband, and a high sensitivity of -152dBm. Through countermeasures against substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external low-noise amplifier.     

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-/spl mu/m CMOS process

A 1-V 24-GHz 17.5-mW fully integrated phase-locked loop employing a transformer-feedback voltage-controlled oscillator and a stacked divide-by-2 frequency divider for low voltage and low power is presented. Implemented in a 0.18-/spl mu/m CMOS process and operated at 24 GHz with a 1-V supply, the PLL measures in-band phase noise of -106.3 dBc at a frequency offset of 100 kHz and out-of-band phase noise of -119.1 dBc/Hz at a frequency offset of 10 MHz. The PLL dissipates 17.5 mW and occupies a core area of 0.55 mm/sup 2/.     

A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process

A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35-/spl mu/m CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.     

A 30-gb/s 70-mW one-stage 4:1 multiplexer in 0.13-/spl mu/m CMOS

A completely integrated 4:1 multiplexer for high-speed operation and low power consumption is presented. The circuit uses a new architecture where four data streams are multiplexed in one stage. Pulses with a duty cycle of 25% switch the inputs to the multiplexer (MUX) output. The pulses are generated from the clock signal and the divided clock signal. Measurement results show the performance of the IQ divider. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. The lower number of gates compared to the conventional tree topology enables low-power design. Relaxed timing conditions are additional benefits of the one-stage MUX topology. The IC is fabricated in a 0.13-/spl mu/m standard bulk CMOS technology and uses 1.5-V supply voltage. The MUX works up to 30 Gb/s and consumes 70 mW.     

Millimeter-wave voltage-controlled oscillators in 0.13-/spl mu/m CMOS technology

This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.     

A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-/spl mu/m CMOS

A 2.1-GHz 1.3-V 5-mW fully integrated Q-enhancement LC bandpass biquad programmable in f/sub o/, Q, and peak gain is implemented in 0.35-/spl mu/m standard CMOS technology. The filter uses a resonator built with spiral inductors and inversion-mode pMOS capacitors that provide frequency tuning. The Q tuning is through an adjustable negative-conductance generator, whereas the peak gain is tuned through an input G/sub m/ stage. Noise and nonlinearity analyses presented demonstrate the design tradeoffs involved. Measured frequency tuning range around 2.1 GHz is 13%. Spiral inductors with Q/sub o/ of 2 at 2.1 GHz limit the spurious-free dynamic range (SFDR) at 31-34 dB within the frequency tuning range. Measurements show that the peak gain can be tuned within a range of around two octaves. The filter sinks 4 mA from a 1.3-V supply providing a Q of 40 at 2.19 GHz with a 1-dB compression point dynamic range of 35 dB. The circuit operates with supply voltages ranging from 1.2 to 3 V. The silicon area is 0.1 mm/sup 2/.     

A 0.6-V 1.6-mW transformer-based 2.5-GHz downconversion mixer with +5.4-dB gain and -2.8-dBm IIP3 in 0.13-/spl mu/m CMOS

On-chip transformers are best suited to lower the supply voltage in RF integrated circuits. A design method to achieve a high current gain with an on-chip transformer operating in resonance is presented. The proposed method will be proven analytically and has been applied to a downconversion mixer. Thereby part of the overall gain of the mixer has been shifted from the RF input stage to the transformer. Thus, the power consumption has been reduced and, in spite of the low supply voltage, moderate linearity has been achieved. Although the transformer has a bandpass behavior, a 3-dB bandwidth of 900 MHz at a center frequency of 2.5 GHz has been achieved. The downconversion mixer has been realized in 0.13-mum CMOS. It consumes 1.6 mW from a 0.6-V supply. A gain of +5.4 dB, a third-order intercept point of -2.8 dBm, an input 1-dB compression point of -9.2 dBm, and a single-sideband noise figure of 14.8 dB have been achieved     

A new Schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals

A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-/spl mu/m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise.     

RF noise in 0.18-/spl mu/m and 0.13-/spl mu/m MOSFETs

Studied the gate finger number and gate length dependence on minimum noise figure (NF/sub min/) in deep submicrometer MOSFETs. A lowest NF/sub min/ of 0.93 dB is measured in 0.18-/spl mu/m MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 /spl mu/m shows larger NFmin than the 0.18-/spl mu/m case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-/spl mu/m MOSFET gives higher NF/sub min/ due to the higher gate resistance and a modified T-gate structure proposed to optimize the NF/sub min/ for further scaling down of the MOSFET.     

192 GHz push-push VCO in 0.13 /spl mu/m CMOS

A 192 GHz cross-coupled push-push voltage controlled oscillator (VCO) is fabricated using the UMC 0.13 /spl mu/m CMOS logic process. The VCO can be tuned from 191.4 to 192.7 GHz. The VCO provides output power of /spl sim/-20 dBm and phase noise of /spl sim/-100 dBc/Hz at 10 MHz offset, while consuming 11 mA from a 1.5 V supply.     

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm/sup 2/ 0.13-/spl mu/m CMOS

This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-/spl mu/m CMOS ADC occupies 0.09 mm/sup 2/ and consumes 21 mW.     

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.     

A 10-bit 400-MS/s 160-mW 0.13-/spl mu/m CMOS dual-channel pipeline ADC without channel mismatch calibration

This paper describes a 10-bit 400-MS/s dual-channel analog-to-digital converter (ADC) insensitive to offset, gain, and sampling-time mismatches between channels. An adaptive closed-loop sampling technique based on a multi-stage amplifier eliminates the channel offset effectively. Multi-stage amplifiers with high DC gain reduce the gain mismatch between channels and guarantee a large signal swing at low supply voltages. A single clock-edge sampling scheme for clock-skew reduction minimizes the sampling-time mismatch. The proposed prototype ADC in a 0.13-/spl mu/m CMOS process occupies an active area of 4.2mm/sup 2/, dissipates 160mW from 1.2 V and 400 MS/s, and shows a signal-to-noise-and-distortion ratio of 54.8 dB with a 29-MHz sinusoidal input at 400 MS/s without any channel-mismatch calibration technique. The measured maximum offset and gain mismatches are less than 0.1% and 0.2%, respectively.     

A 9-50-GHz Gilbert-cell down-conversion mixer in 0.13-/spl mu/m CMOS technology

A broadband microwave/millimeter-wave (MMW) Gilbert-cellmixer using standard 1P8M 0.13-/spl mu/m complementary metal oxide semiconductor (CMOS) technology is presented in this letter. Two radio frequency (RF) transformer baluns are used in RF-and local oscillator (LO)-ports to convert single-ended signals to differential signals. Thin film microstrip line is employed for the matching networks and transformer design. This mixer has a conversion gain of better than 5dB from 9 to 50GHz. Between 5 and 50GHz,the RF- and LO-to-intermediate frequency (IF) isolations are better than 40dB. The RF-to-LO and LO-to-RF isolations are all better than 20dB. To the authors' knowledge, this is the first CMOS Gilbert-cell mixer operating to MMW frequency to date.     

A direct-conversion receiver IC for WCDMA mobile systems

A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.