Improved Thermal Behavior of Multiple Linked Arrays of Silicon Nanowires Integrated into Planar Thermoelectric Microgenerators

Low-dimensional structures have been shown to be promising candidates for enhancing the thermoelectric properties of semiconductors, paving the way for integration of thermoelectric generators into silicon microtechnology. With this aim, dense arrays of well-oriented and size-controlled silicon nanowires (Si NWs) obtained by the chemical vapor deposition (CVD)-vapor–liquid–solid (VLS) mechanism have been implemented into microfabricated structures to develop planar unileg thermoelectric microgenerators (μTEGs). Different low-thermal-mass suspended structures have been designed and microfabricated on silicon-on-insulator (SOI) substrates to operate as microthermoelements using p-type Si NW arrays as the thermoelectric material. To obtain nanowire arrays with effective lengths larger than normally attained by the VLS technique, structures composed of multiple ordered arrays consecutively bridged by transversal microspacers have been fabricated. The successive linkage of multiple Si NW arrays enabled the development of larger temperature differences while preserving good electrical contact. This gives rise to small internal thermoelement resistances, enhancing the performance of the devices as energy harvesters.     

High-Temperature Performance of Stacked Silicon Nanowires for Thermoelectric Power Generation

Deep reactive-ion etching at cryogenic temperatures (cryo-DRIE) has been used to produce arrays of silicon nanowires (NWs) for thermoelectric (TE) power generation devices. Using cryo-DRIE, we were able to fabricate NWs of large aspect ratios (up to 32) using a photoresist mask. Roughening of the NW sidewalls occurred, which has been recognized as beneficial for low thermal conductivity. Generated NWs, which were 7 μm in length and 220 nm to 270 nm in diameter, were robust enough to be stacked with a bulk silicon chip as a common top contact to the NWs. Mechanical support of the NW array, which can be created by filling the free space between the NWs using silicon oxide or polyimide, was not required. The Seebeck voltage, measured across multiple stacks of up to 16 bulk silicon dies, revealed negligible thermal interface resistance. With stacked silicon NWs, we observed Seebeck voltages that were an order of magnitude higher than those observed for bulk silicon. Degradation of the TE performance of silicon NWs was not observed for temperatures up to 470°C and temperature gradients up to 170 K.     

Analysis of Thermoelectric Properties of Scaled Silicon Nanowires Using an Atomistic Tight-Binding Model

Low-dimensional materials provide the possibility of improved thermoelectric performance due to the additional length scale degree of freedom for engineering their electronic and thermal properties. As a result of suppressed phonon conduction, large improvements in the thermoelectric figure of merit, ZT, have recently been reported in nanostructures, compared to the raw materials. In addition, low dimensionality can improve a device’s power factor, offering an additional enhancement in ZT. In this work the atomistic sp³d⁵s* spin-orbit-coupled tight-binding model is used to calculate the electronic structure of silicon nanowires (NWs). The Landauer formalism is applied to calculate an upper limit for the electrical conductivity, the Seebeck coefficient, and the power factor. We examine n-type and p-type nanowires with diameters from 3 nm to 12 nm, in [100], [110], and [111] transport orientations, at different doping concentrations. Using experimental values for the lattice thermal conductivity in nanowires, an upper limit for ZT is computed. We find that at room temperature, scaling the diameter below 7 nm can at most double the power factor and enhance ZT. In some cases, however, scaling does not enhance the performance at all. Orientations, geometries, and subband engineering techniques for optimized designs are discussed.     

Fabrication of High-Temperature-Stable Thermoelectric Generator Modules Based on Nanocrystalline Silicon

High-temperature-stable thermoelectric generator modules (TGMs) based on nanocrystalline silicon have been fabricated, characterized by the Harman technique, and measured in a generator test facility at the German Aerospace Center. Starting with highly doped p- and n-type silicon nanoparticles from a scalable gas-phase process, nanocrystalline bulk silicon was obtained using a current-activated sintering technique. Electrochemical plating methods were employed to metalize the nanocrystalline silicon. The specific electrical contact resistance ρ _c of the semiconductor–metal interface was characterized by a transfer length method. Values as low as ρ _c < 1 × 10^?6 Ω cm² were measured. The device figure of merit of a TGM with 64 legs was approximately ZT = 0.13 at 600°C as measured by the Harman technique. Using a generator test facility, the maximum electrical power output of a TGM with 100 legs was measured to be roughly 1 W at hot-side temperature of 600°C and cold-side temperature of 300°C.     

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a $hbox{Si} hbox{p}^{+}{-}hbox{i}{-} hbox{n}^{+}$ tunneling junction, the TFET with a gate length of $sim$200 nm exhibits good subthreshold swing of $sim$ 70 mV/dec, superior drain-induced-barrier-lowering of $sim$ 17 mV/V, and excellent $I_{rm on} {-} I_{rm off}$ ratio of $sim!!hbox{10}^{7}$ with a low $I_{rm off} (sim!!hbox{7} hbox{pA}/muhbox{m})$. The obtained 53 $muhbox{A}/muhbox{m} I_{rm on}$ can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.      

Nanograin Effects on the Thermoelectric Properties of Poly-Si Nanowires

In this work we perform a theoretical analysis of the thermoelectric performance of polycrystalline Si nanowires (NWs) by considering both electron and phonon transport. The simulations are calibrated with experimental data from monocrystalline and polycrystalline structures. We show that heavily doped polycrystalline NW structures with grain size below 100 nm might offer an alternative approach to achieve simultaneous thermal conductivity reduction and power factor improvements through improvements in the Seebeck coefficient. We find that deviations from the homogeneity of the channel and/or reduction in the diameter may provide strong reduction in the thermal conductivity. Interestingly, our calculations show that the Seebeck coefficient and consequently the power factor can be improved significantly once the polycrystalline geometry is properly optimized, while avoiding strong reduction in the electrical conductivity. In such a way, ZT values even higher than the ones reported for monocrystalline Si NWs can be achieved.     

硅纳米线的电学特性

总结了硅纳米线在电学特性方面的研究进展,重点分析了本征及掺杂硅纳米线的载流子浓度与迁移率、场发射及电子输运特性。研究表明通过对硅纳米线进行掺杂可提高载流子浓度及迁移率、场发射和电子输运性能,随硅纳米线直径的减小其电学性能增强。因此,硅纳米线在场效应晶体管及存储元件等纳米器件方面具有极大的应用前景。     

基于微缩雷达应用的硅基毫米波片上天线

为研究小型化、微型化天线在现代无线应用中的集成趋势,对当前工艺水平下的毫米波段片上天线(AoC)设计进行了总结。从集成角度,对单片集成和混合集成的概念分别进行了优劣比较和讨论。作为一个单片集成技术方案的可靠候选,对硅基单片毫米波集成电路(SIMMWIC)技术进行了介绍,并给出了利用该技术实现的整流天线例子。通过单片集成的雪崩二极管发射机展示了如何利用三维电磁仿真工具设计及证明片上天线的性能,利用仿真和实际验证探讨了硅基毫米波片上天线的挑战和方法,为小型化雷达系统方案提供了一个稳固的基础。     

Measurement of Thermoelectric Properties of Single Semiconductor Nanowires

We have measured the thermopower and the thermal conductivity of individual silicon and indium arsenide nanowires (NWs). In this study, we evaluate a self-heating method to determine the thermal conductivity λ. Experimental validation of this method was performed on highly n-doped Si NWs with diameters ranging from 20 nm to 80 nm. The Si NWs exhibited electrical resistivity of $\rho = (8\pm4)\, \hbox{m}\Upomega\,\hbox{cm}$ ρ = ( 8 ± 4 ) m Ω cm at room temperature and Seebeck coefficient of ?(250 ± 100) μV/K. The thermal conductivity of Si NWs measured using the proposed method is very similar to previously reported values; e.g., for Si NWs with 50 nm diameter, λ = 23 W/(m K) was obtained. Using the same method, we investigated InAs NWs with diameter of 100 nm and resistivities of $\rho = (25\pm5)\, \hbox{m}\Upomega\,\hbox{cm}$ ρ = ( 25 ± 5 ) m Ω cm at room temperature. Thermal conductivity of λ = 1.8 W/(m K) was obtained, which is about 20 to 30 times smaller than in bulk InAs. We analyzed the accuracy of the self-heating method by means of analytical and numerical solution of the one-dimensional (1-D) heat diffusion equation taking various loss channels into account. For our NWs suspended from the substrate with low-impedance contacts the relative error can be estimated to be ≤25%.     

Band-Structure Effects in Ultrascaled Silicon Nanowires

In this paper, we investigate band-structure effects on the transport properties of ultrascaled silicon nanowire FETs operating under quantum-ballistic conditions. More specifically, we expand the dispersion relationship epsiv(kappa) in a power series up to the third order in kappa² and generate the corresponding higher order operator to be used within the single-electron Hamiltonian for the solution of the Schrodinger equation. We work out a hierarchy of nonparabolic models accounting for the following: 1) the shift of the subband edges and the change in the transport effective masses; 2) the higher order Hamiltonian operator; and 3) the splitting of the fourfold unprimed subbands in nanometer-size FETs. We then compute the device turn-on characteristics, the threshold shift versus diameter, and the subthreshold slope (SS) versus gate length. By compensating for the different threshold voltages, i.e., by reducing the turn- on characteristics to the same leakage current at zero gate bias, it turns out that the current discrepancies between the most general model and the bulk-parabolic model are contained within 20%. Finally, it turns out that the nonparabolic band structure gives an improved SS at the lowest gate lengths due to a reduced source-drain tunneling, reaching up to 30% enhancement.     

火焰水解法制作SiO2平面波导材料

采用火焰水解法在Si基上淀积SiO2/GeO2:SiO2预制材料,然后在真空中／空气气氛中高温处理（1380℃）后,制得玻璃化的SiO2/GeO2:SiO2膜材料。该材料膜厚适中（10－30μm）、平整度好、光滑透明和适合制作单模、多模列平面小光栅。利用XRD,SEM和台阶仪等仪器对SiO2膜进行了测试分析。     

Scalable Silicon Nanostructuring for Thermoelectric Applications

The current limitations of commercially available thermoelectric (TE) generators include their incompatibility with human body applications due to the toxicity of commonly used alloys and possible future shortage of raw materials (Bi-Sb-Te and Se). In this respect, exploiting silicon as an environmentally friendly candidate for thermoelectric applications is a promising alternative since it is an abundant, ecofriendly semiconductor for which there already exists an infrastructure for low-cost and high-yield processing. Contrary to the existing approaches, where n/p-legs were either heavily doped to an optimal carrier concentration of 10¹⁹ cm^?3 or morphologically modified by increasing their roughness, in this work improved thermoelectric performance was achieved in smooth silicon nanostructures with low doping concentration (1.5 × 10¹⁵ cm^?3). Scalable, highly reproducible e-beam lithographies, which are compatible with nanoimprint and followed by deep reactive-ion etching (DRIE), were employed to produce arrays of regularly spaced nanopillars of 400 nm height with diameters varying from 140 nm to 300 nm. A potential Seebeck microprobe (PSM) was used to measure the Seebeck coefficients of such nanostructures. This resulted in values ranging from ?75 μV/K to ?120 μV/K for n-type and 100 μV/K to 140 μV/K for p-type, which are significant improvements over previously reported data.     

Inkjet Printing Flexible Thermoelectric Devices Using Metal Chalcogenide Nanowires

Development of flexible thermoelectric devices offers exciting opportunities for wearable applications in consumer electronics, healthcare, human–machine interface, etc. Despite the increased interests and efforts in nanotechnology-enabled flexible thermoelectrics, translating the superior properties of thermoelectric materials from nanoscale to macroscale and reducing the manufacturing costs at the device level remain a major challenge. Here, an economic and scalable inkjet printing method is reported to fabricate high-performance flexible thermoelectric devices. A general templated-directed chemical transformation process is employed to synthesize several types of 1D metal chalcogenide nanowires (e.g., Ag₂Te, Cu₇Te₄, and Bi₂Te_2.7Se_0.3). These nanowires are made into inks suitable for inkjet printing by dispersing them in ethanol without any additives. As a showcase for thermoelectric applications, fully inkjet-printed Ag₂Te-based flexible films and devices are prepared. The printed films exhibit a power factor of 493.8 µW m⁻¹ K⁻² at 400 K and the printed devices demonstrate a maximum power density of 0.9 µW cm⁻² K⁻², both of which are significantly higher than those reported in state-of-the-art inkjet-printed thermoelectrics. The protocols of metal chalcogenide ink formulations, as well as printing are general and extendable to a wider range of material systems, suggesting the great potential of this printing platform for scalable manufacturing of next-generation, high-performance flexible thermoelectric devices.     

Si纳米线及其器件研究进展

Si纳米线是一种非常重要的一维半导体纳米材料,在纳米器件方面有很好的应用前景。综述了Si纳米线的一些重要制备方法:激光烧蚀法、模板法、化学气相生长法、热蒸发法,简要介绍了各种制备方法过程并分析各种方法制备纳米线的优缺点。还介绍了Si纳米线所制备纳米器件的电学、电子输运等特性,说明了掺硼、掺磷纳米线分别具有p型、n型半导体特征。最后介绍了Si纳米线在电子器件、纳米线电池、传感器方面的相关应用。     

Charge Transport Characteristics in Boron-Doped Silicon Nanowires

We report the charge transport and inferred surface depletion characteristics of silicon nanowires (Si NWs) with diameters of 90–170 nm after boron doping to $hbox{8}times hbox{10}^{17}$ and $hbox{4} times hbox{10}^{19} hbox{cm}^{-3}$ by a proximity diffusion doping technique. Four-probe current–voltage measurements were performed to obtain the NW resistivity, and the electrically active dopant concentration and surface oxide charge density were extracted by varying the NW diameter. The Ti/Au to Si NW contact resistance and specific contact resistivity were also obtained, and specific contact resistivities as low as $hbox{2} times hbox{10}^{-5} Omega cdot hbox{cm}^{2}$ were achieved. The derived parameters for these ex situ boron-doped Si NWs agree reasonably well with the expected characteristics and earlier reported results for in situ boron-doped Si NWs. Interface charge creates a surface depletion region in p-type Si NWs, which decreases the conducting area of the NW. This effect increases the NW resistance and becomes increasingly significant with decreasing dopant concentration and NW diameter. A simple method is presented to estimate the relative influence of surface charge density on electrical transport in NWs for this case.      

硅纳米线的掺杂工艺与检测

掺杂硅纳米线有可能成为一种重要的硅纳米电子器件材料。因而,硅纳米线的掺杂工艺与检测很重要。半导体的掺杂工艺主要为扩散法,而硅纳米半导体线的掺杂检测方法主要包括电流-电压法、拉曼光谱、光致发光(PL)光谱、X-射线光电子能谱(XPS)及近边X-射线吸收精细结构光谱(NEXAFS)等。该文介绍了可引入到硅纳米线研究的现有半导体的掺杂工艺及检测方法,并就硅纳米线的掺杂工艺及检测的最新进展做作了详细的讨论。     

Atomic Insights of Self-Healing in Silicon Nanowires

The self-healing capability is highly desirable in semiconductors to develop advanced devices with improved stability and longevity. In this study, the automatic self-healing in silicon nanowires is reported, which are one of the most important building blocks for high-performance semiconductor nanodevices. A recovery of fracture strength (10.1%) on fractured silicon nanowires is achieved, which is demonstrated by in situ transmission electron microscopy tensile tests. The self-healing mechanism and factors governing the self-healing efficiency are revealed by a combination of atomic-resolution characterizations and atomistic simulations. Spontaneous rebonding, atomic rearrangement, and van der Waals attraction are responsible for the self-healing in silicon nanowires. Additionally, the self-healing efficiency is affected by the fracture surface roughness, the nanowire size, the nanowire orientation, and the passivation of dangling bonds on fracture surfaces. These new findings shed light on the self-healing mechanism of silicon nanowires and provide new insights into developing high-lifetime and high-security semiconductor devices.