Implementation of digital filtering algorithms using pipelined vector processors

The implementation of digital filtering algorithms using pipelined vector processors is investigated. Modeling of vector processors and vectorization methods are explained, and then the performances of several implementation methods are evaluated based on the model. Vector processor implementation of FIR filtering algorithms using the outer product method and the indirect convolution method is evaluated. Recursive and adaptive filtering algorithms, which lead to dependency problems in direct vector processor implementations, are implemented very efficiently using a newly developed vectorization method. The proposed method computes multiple output samples at a time, making the vector length independent of the filter order. Illustrative examples comparing theoretical results with Cray X-MP simulation results are included.     

Implementation of space-time equalizer using multiplesingle-constrained SMI array processors and MLSE

We implemented a space-time equalizer using two sets of single-constrained sample matrix inversion array processors and a maximum-likelihood sequence estimator by using digital signal processors and field-programmable gate arrays. One of the array processors constrains the direct path, sends the one-symbol-delayed path component to the array output, and suppresses the paths with longer delays. The other array processor constrains the one-symbol-delayed path, sends the direct path component to the array output, and also suppresses the paths with longer delays. The desired paths, thus, extracted, whose signal-to-interference-plus-noise-ratios are improved in both path-diversity branches, are then combined by using a branch-metric-combining Viterbi equalizer. We implemented a receiver equipped with this equalizer and evaluated its bit-error rate performance by using a channel emulator. Experimental results indicate that the space-time equalizer provides both space diversity gains and path diversity gains while suppressing signals on paths with long delays     

一种新的减少媒体处理器中寄存器文件复杂度的方法

寄存器文件被广泛地应用于最新的DSP和媒体处理器的设计,为了能够减小处理器所开销的芯片面积、功耗以及体系结构的复杂度,必须合理设计寄存器文件结构.本文通过对现行采用的几种寄存器文件结构的分析对比,提出了一种新的独立寄存器文件单元结构,即将寄存器文件作为一个流水级单元,并且通过编译器静态调度的方法实现了寄存器文件端口数的减少以及旁路电路的简化.从实验的结果可以看出,这种结构不仅能满足媒体处理器的目标要求,而且对VLIW结构的媒体处理器有重要的意义.     

Implementation of matrix decomposition structures of 2-D digital filters via VLSI array processors

This paper describes an implementation of 2-D FIR and IIR linear digital filters via VLSI array processors. The underlying realization structures are based on the matrix decomposition approach. The 2-D concurrent processing is used in order to implement the row and column delays within the cycle time. A high degree of concurrency is achieved by exploiting the pipelining of the array processors with the inherent parallelism of the matrix decomposition structure. The resulting structures are modular, and regular, use only local communication and internal local feedback loops, and achieve high throughput and sampling rates.     

Communication processors

A review is given of the use of small digital computers for the processing of data received over communication lines. A detailed discussion is presented of the hardware and software requirements of front-end processors, network processors, remote data concentrators, and message switching systems. Finally, the desirable features common to all communications processors are analyzed. Examples of actual applications are given, so that a realistic basis can be established for the determination of the features which should be included in the design of new communication processors.     

用户可定制的处理器

随着130nm和90nm工艺的成熟,每平方毫米的硅片面积上可以集成大约100K～200K的逻辑门,一颗面积大约50mm2的低成本芯片可以容纳5M～10M逻辑门.越来越多的SoC设计者正在试图将整个系统集成在一颗芯片上,但是他们也面临着严峻的挑战,因为传统的基于RTL的SoC硬件设计方法的缺点正日益显现出来.     

Telecommunications processors

Telecommunications controllers worldwide are becoming increasingly stored-program oriented. Electromechanical and electronic wired logic controllers lack the flexibility, maintainability, and (ultimately) the economy of stored program processors. While similar to commercial computers, most stored program telecommunications processors have features unique either in nature or degree of application. There also exists a remarkable variety of overall architectural features which are useful in telecommunications applications, and a similar variety of administrations and manufacturers willing to espouse them. Pertinent stored program processor architectural features are discussed as a dass, then extant and proposed processors are described and placed in perspective, Finally, likely future trends are discussed.     

Changing processors

The author reports on the theory and practice behind an innovative 32 bit RISC processor core, whose architecture can be customised to provide the optimum design solution for processor-based application-specific integrated circuits. In its basic configuration, the ARC processor, the Tangent-A4, is a four-stage pipeline device, with instructions, data and address formats all 32 bit. It also boasts separate instruction and data buses (Harvard architecture), data and instruction caches, and a unique host interface (parallel, JTAG or user defined), giving external devices access to the internal registers and memory     

Multimedia processors

This paper describes large-scale-integration programmable processors designed for multimedia processing such as real-time compression and decompression of audio and video as well as the generation of computer graphics. As the target of these processors is to handle audio and video in real time, the processing capability must be increased tenfold compared to that of conventional microprocessors, which were designed to handle mainly texts, figures, tables, and photographs. To clarify the advantages of a high-speed multimedia processing capability, we define these chips as multimedia processors. General-purpose microprocessors for workstations and personal computers (PCs) use special built-in hardware for multimedia processing, so the multimedia processors described include these modified general-purpose microprocessors. After reviewing the history of programmable processors, we classify multimedia processors into five categories depending on their basic architecture. The categories are reduced instruction set computer (RISC) microprocessors for workstations, complex instruction set computer microprocessors for PCs, embedded RISCs, low-power digital signal processors (DSPs), which are mainly used for mobile communications devices, and media processors that support PCs for multimedia applications. These five classes are then grouped into two: microprocessors with a multimedia instruction set and highly parallel DSPs. An architectural comparison between these two groups on the basis of Moving Picture Experts Group decoding applications is made, and the advantages and disadvantages of each class are clarified. Future processors, including “system on a chip,” and their applications are also discussed     

软硬件协同减少媒体处理器中寄存器文件写次数的方法

在嵌入式系统的应用中,程序代码中存在着相当多的局部变量,这些局部变量的使用范围(生存期)通常都很小.相关指令在流水中需要局部变量的值可以直接从旁路逻辑中得到,并在流水中完成局部变量值的全部使用.对这种局部变量就没有必要将流水输出结果写回寄存器文件,以减少对寄存器文件(RF)的读写操作次数,从而降低对寄存器文件端口的读写要求.决定是否将结果写回寄存器文件的关键的是要确定寄存器的生存期以及流水中旁路逻辑的情况,本文根据所设计的媒体处理器提出了一种确定程序代码中寄存器生存期的算法,并通过指令编码实现对硬件结构的使能控制,即对流水输出结果写回寄存器文件的控制.软件仿真结果表明,对DSP中不同的应用程序平均可以减少94%的寄存器文件写次数.     

媒体分发服务器NAT穿越的实现

媒体分发服务器是网络视频监控平台中负责流媒体分发的重要模块.网络地址转换器 (Network Address Translator,NAT)能很好地解决IPv4地址资源匮乏的问题,但同时也给各个私网用户之间或私网与公网用户之间的通信带来了障碍.文章主要介绍这种NAT障碍的形成,并给出了会话初始协议(SIP)下媒体分发服务器实现NAT穿越的一种方案.     

Implementation of physical and media access protocols forhigh-speed networks

Existing protocols for high-speed local area networks (HSLANs) and metropolitan area networks (MANs) are dealt with from an implementation standpoint. Emphasis is put on the lowest layers of the ISO OSI (Open Systems Interconnection) Reference Model, i.e. the physical layer and media access control sublayer of the data-link layer. Seven representative state-of-the-art HSLAN and MAN media-access protocols are surveyed and classified, and implementations of these protocols that are used in prototype and commercial networks are analyzed. The complexity, technology, and performance of the implementation are described and compared     

A survey of multicore processors

General-purpose multicore processors are being accepted in all segments of the industry, including signal processing and embedded space, as the need for more performance and general-purpose programmability has grown. Parallel processing increases performance by adding more parallel resources while maintaining manageable power characteristics. The implementations of multicore processors are numerous and diverse. Designs range from conventional multiprocessor machines to designs that consist of a "sea" of programmable arithmetic logic units (ALUs). In this article, we cover some of the attributes common to all multicore processor implementations and illustrate these attributes with current and future commercial multicore designs. The characteristics we focus on are application domain, power/performance, processing elements, memory system, and accelerators/integrated peripherals.     

Directions in DSP processors

The evolution of single-chip digital signal-processor (DSP) architectures is discussed. It is argued that multiple arithmetic units and functionally enhanced arithmetic units are promising directions for further evolution of the datapath architecture. Candidate structures are defined, and the operation of popular DSP benchmarks on these structures is demonstrated     

Elaborated rank order processors

The author discusses an elaborated rank order processor, which admits constants as operands and preliminary operations on input variables (e.g. negation) so that the processor is also implementable in bit-serial, most significant bit leading, terms. The theory for the special case in which the constant 0 and the operation negation are admitted and a realization in finite autoregressive form exists is discussed. Input/output relations are expressible with a finite-state sequential machine with ternary inputs and outputs; that machine is only a mathematical construct and need not represent an actual device. The question of root signals is examined theoretically and by example. An example showing a bandpass effect is presented, and computer programs for doing the relevant calculations pertaining to finite automata and simulations are offered. A part of a theory for general elaboration is also presented     

Initializing RAM-based logarithmic processors

A logarithmic processor is proposed that uses external RAM for holding the table required for logarithmic subtraction. The proposed processor requires that the RAM be initialized before any computations occur. We give an algorithm to initialize the RAM using the limited arithmetic unit of the processor. The algorithm is ten times faster than a bit by bit computation of the logarithm and antilogarithm. Bounds are developed for comparing the error of this algorithm against the error of earlier algorithms. Simulation results show that this algorithm avoids catastrophic cancellation, and is as accurate as any previously known single precision algorith.     

Fourier optical signal processors

Progress in Fourier optical processing techniques is reviewed. Particular emphasis is placed on real-time pattern recognition, which recently has received increased interest as the result of new filter formulations that can be implemented with existing spatial light modulators. Architectures for coherent optical correlation are reviewed, as are the recently reported phase-only filters. Smart filters that attack the inherent distortion sensitivity of correlation, including those suitable for implementation with phase-only modulation, are reviewed. Correlation experiments implementing real-time variation of both input and reference patterns are also reviewed. The potential for successful near-term application of these techniques is examined     

The evolution of DSP processors

The number and variety of products that include some form of digital signal processing (DSP) has grown dramatically. DSP has become a key component in many consumer, communications, medical, and industrial products, which use a variety of hardware approaches to implement DSP, ranging from the use of off-the-shelf microprocessors to field-programmable gate arrays (FPGAs) to custom integrated circuits (ICs). Programmable “DSP processors”, a class of microprocessors optimized for DSP, are a popular solution for several reasons: they can potentially be reprogrammed in the field, allowing product upgrades or fixes. They are often more cost-effective (and less risky) than custom hardware, particularly for low-volume applications, where the development cost of custom ICs may be prohibitive. In comparison to other types of microprocessors, DSP processors often have an advantage in terms of speed, cost, and energy efficiency. In this article, we trace the evolution of DSP processors from early architectures to current state-of-the-art devices. We highlight some of the key differences among architectures and compare their strengths and weaknesses. Finally, we discuss the growing class of general-purpose processors that have been enhanced to address the needs of DSP applications