模拟集成电路模块版图的生成系统

介绍了模拟集成电路模块版图的开发系统.系统用高效的过程化版图描述语言构造模拟模块,编译产生与工艺及应用无关的模块版图生成器.系统的网络识别和模块内布线功能自动完成模块网络的完全连通,基于优选的电气特性驱动版图生成,提高设计可靠性.该系统已辅助设计出多个高性能集成运算放大器、模拟开关等芯片版图.     

A performance-driven placement tool for analog integrated circuits

This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction. During each iteration of the simulated annealing algorithm, the layout-induced performance degradation is calculated from the geometrical properties of the intermediate solution. The placement tool inherently handles symmetry constraints, circuit loading effects and device mismatches. The feasibility of the approach is demonstrated with practical circuit examples     

ISAAC: a symbolic simulator for analog integrated circuits

The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The program's capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm     

Automated topology synthesis of analog and RF integrated circuits: A survey

The puzzle of automatically synthesizing analog and radio frequency (RF) circuit topology has not yet been offered with an industrially-acceptable solution although endeavors still continue to seek a conquest in this area. This survey provides a comprehensive study of the techniques utilized for this purpose. The existing methods are analyzed from four different viewpoints, namely, structural view, conceptual view, implementation view, and application view. Different schemes are perused with their advantages and drawbacks discussed in the context of balanced performance between configuration-space coverage and search efficiency. Some prospective trends are pointed out to shed light on the upcoming research activities.     

Specifics of electromagnetic radiation effects on integrated circuits

Modern regulations [1] stress the necessity of testing integrated circuits (ICs) in order to determine the real level of their resistance to single voltage pulses induced by electromagnetic radiation (EMR). With expansion of the EMR spectral composition, however, direct energy release can occur due to the absorption of the EMR field energy by the IC chip itself. To assess this possibility, the relationship is found between different mechanisms of the EMR-induced energy release for the typical irradiation geometry.     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

CMOS analog integrated circuits based on weak inversion operations

A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.     

Current-mode CMOS integrated circuits for analog computation and signal processing: A tutorial

This paper presents an overview of design techniques for a broad range of current-mode analog integrated circuits implemented in CMOS technology at a tutorial level. Primarily, emphasis is placed on circuit configurations, first-order analysis, and approximate design equations for analog integrated circuits operating in current domain for signal computation and processing applications.     

Hierarchical yield estimation of large analog integrated circuits

A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive     

MOSFET thermal noise modeling for analog integrated circuits

The effects of device geometry, oxide thickness, and bias condition on the thermal noise of MOSFET's are investigated. The experimental results show that the conventional MOSFET thermal noise models do not accurately predict the thermal noise of MOSFET's. A model that is capable of predicting the thermal noise of both long and short channel devices in both the triode and saturation regions is presented. This model, which can be easily implemented into existing circuit simulators such as SPICE, has been verified by a wide variety of measurements     

Design principles for low-voltage low-power analog integrated circuits

In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.     

Potential of MOS technologies for analog integrated circuits

Reviews the rapid progress in MOS analog circuit techniques over the past three years, and attempts to estimate the near-term attainable characteristics of MOS LSI circuits which incorporate both analog and digital functions.     

A manufacturing process for analog and digital gallium arsenide integrated circuits

A process for manufacturing small-to-medium scale GaAs integrated circuits is described. Integrated FET's, diodes, resistors, thin-film capacitors, and inductors are used for monolithic integration of digital and analog circuits. Direct implantation of Si into > 10⁵Ω.cm resistivity substrates produces n-layers with ± 10-percent sheet resistance variation. A planar fabrication process featuring retained anneal cap (SiO2), proton isolation, recessed Mo-Au gates, silicon nitride passivation, and a dual-level metal system with polyimide intermetal dielectric is described. Automated on-wafer testing at frequencies up to 4 GHz is introduced, and a calculator-controlled frequency domain test system described. Circuit yields for six different circuit designs are reported, and process defect densities are inferred.     

Failure physics of integrated circuits — A review

This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems.In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four groups according to their origin: (i) failure modes associated with chip; (ii) failure modes resulting from leads and bonds; (iii) failure modes associated with encapsulation; and (iv) failure modes due to external effects and overstress. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on failure mode distributions are discussed.In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. Also, the role of electrical testing by the curve tracer and the accompanying analytical techniques (scanning electron microscopy, transmission electron microscopy, electron beam microprobe, Auger electron spectroscopy and X-ray radiograph) are discussed. Finally, the diagnostic technique is described which, using simple electrical testing by the curve tracer and some tests for enhancing of the failure modes (high temperature bake and high temperature burn-in), enables simple detection of integrated circuit failure modes.In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First, the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.     

A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Applying symbolic techniques for analog circuit analysis is a traditional research subject, which has lasted for over half a century. The past decade has witnessed a significant advancement of the symbolic techniques developed specifically for large analog integrated circuits. The key methodology introduced is a data structure called binary decision diagram (BDD) which was established originally for logic design and verification. The application of the BDD technique for analog circuit analysis has the following features: (1) It is a compact data structure so that data redundancy in symbolic analysis can be eliminated. (2) It provides a mechanism for implicit enumeration method so that exhaustive enumeration commonly performed in symbolic analysis can be avoided. (3) Numerical evaluation on a BDD can be made extremely efficient, making it an excellent means for repetitive analysis. More advanced features are yet to be explored. This survey brings together the significant research results published in the past decade and provides a tutorial overview on the basic principles of applying BDD to analog circuit analysis. Some new directions that are potentially valuable for developing future analog design automation tools are discussed and a design example is given to illustrate the application of symbolic techniques.     

A simple but efficient analog computer for simulation of high-speed integrated circuits

An analog computer is described which performs transient simulation of nonsaturated transistor circuits with little expense of time. The computer contains models of bipolar transistors and Schottky-barrier diodes as well as variable capacitors and resistors, all realized in plug-in technique. The parameters of the semiconductor devices are directly and continuously adjustable. Therefore, no special knowledge is required to operate the computer. For the display, a dual-trace oscilloscope with low bandwidth is sufficient because the analog time range lies above 0.1 ms. Compared with the digital computer simulation, this analog method has the advantages of lower costs and less simulation time, the latter allowing fast interaction between designer and computer. The good accuracy of the described simulation method is demonstrated by comparing the simulated and the directly measured transient response of an integrated subnanosecond E/SUP 2/CL gate. Also it is shown how the delay time of this gate depends on the transistor parameters.     

A method to predict harmonic distortion in small-geometry MOS analog integrated circuits

A method to predict the small-signal linear gain and level of harmonic distortion in analog MOS circuits is presented. This method, based on a generalized nonlinear transfer function approach, lends itself to implementation in the AC small-signal analysis routine of the circuit simulation program SPICE. A low-frequency nonlinear distortion model based on the CSIM simulator MOSFET model is applied to three simple MOSFET circuits. Results presented emphasize the need to consider small-signal quantities in the development of MOSFET models and in the determination of device parameters. The method can be easily extended to include capacitive effects and a prediction of intermodulation distortion.     

Behavior of analog MOS integrated circuits at high temperatures

Thermal effects on small-signal characteristics of MOS transistors are studied and parameters of MOS amplifiers operating at high temperatures are calculated. The predicted performance has been experimentally verified and high-temperature measurements of an operational amplifier and a switched-capacitor precision amplifier are presented.