A CMOS rectifier-integrator for amplitude detection in hard diskservo loops

In this paper a CMOS alternative amplitude detection system is presented. It is designed as an alternative for the, bipolar, amplitude detection in hard disk servo systems. The amplitude is detected by converting the input voltage to a current, rectifying the current, and integrating it on a capacitor. For this a new OTA topology and a rectifier cell are designed. This circuitry is expanded with a very linear current mirror and an automatic offset compensation system to cope with technology spread. The measured accuracy of the amplitude detector is 0.2% (9 b). This makes the circuit suitable for implementation in state-of-the art hard disk systems with very high track densities and very short access times. Because the circuit is realized in standard CMOS it is a further step toward CMOS only hard disk electronics. Because the circuit operates from a single 3 V power supply and has limited power consumption it can be used in battery powered systems     

A 10-bit video BiCMOS track-and-hold amplifier

A 1.2-μm VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between ±4 V. The circuit operates from ±5-V power supplies and is capable of driving a 50-Ω load with ±1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications     

Monolithic integration of a 5.3 GHz regenerative frequency divider using a standard bipolar technology

A monolithic microwave frequency divider IC with an operating range of 1.4?5.3 GHz was developed and fabricated in a standard bipolar technology. The circuit operates on the principle of `regenerative frequency division?. Compared to the most popular divider concepts based on a master-slave D-flip-flop, an almost twice as high input frequency can be divided, provided that the same technology is used. A further advantage is the low power consumption.     

A microprogrammable real-time video signal processor (VSP) formotion compensation

A video signal processor (VSP) LSI circuit with a three pipelined architecture has been developed for pattern matching, which is fundamental for the motion compensation necessary for teleconferencing systems. A high-speed arithmetic logic unit with absolute-value calculation capability and a minimum/maximum value detector, which are essential to pattern matching, have been integrated on the VSP LSI. The chip was fabricated with a 2.5-μm CMOS and double-layer metallization technology. The number of MOSFETs integrated on the 9.91×9.50-mm ² chip is about 48000. It operates at a 14.3-MHz clock frequency with a single 5-V power supply and typically consumes 240 mW. An experimental video signal processing system, using a single VSP LSI chip, is discussed     

An 8-bit video ADC incorporating folding and interpolation techniques

A flash-type analog-to-digital converter that operates without a sample-and-hold circuit and incorporates folding and interpolation techniques is presented. It achieves an excellent performance while dissipating only 300 mW from a single 5-V power supply. The folding and interpolation system and the corresponding block diagram are explained. Implementation of folding and interpolation circuitry and the design of the reference resistor are discussed in detail. Several advantages of the system are investigated. The effective resolution of the converter is given as a function of analog input frequency. An 8-bit resolution bandwidth of 8 MHz is achieved. Up to an analog input frequency of 5 MHz, every distortion component stays below -60 dB. The maximum sample rate is 55 MHz. The circuit occupies 6 mm/SUP 2/ of silicon area, bonding pads included. It is realized in a 2.5-/spl mu/m bipolar process with an f/SUB T/ of 7.5 GHz.     

A 1.8-GHz self-calibrated phase-locked loop with precise I/Qmatching

This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-μm CMOS technology. The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO). A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused by the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.20. The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply     

A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique

A near-infrared heart-rate measurement IC that processes the photoplethysmographic signal was designed using a 0.35-/spl mu/m CMOS technology. The IC consists of a current-to-voltage (I-V) converter, a buffer, a sample-and-hold circuit, a second-order continuous-time low-pass filter (CT-LPF), a comparator, and a timing circuit that is used to pulse the external light-emitting diode with a very low duty cycle to reduce its power consumption. The current steering technique is employed in the design of the CT-LPF to meet the requirement for very low cutoff frequency. The circuit operates from a 3-V lithium battery, occupies a core area of 0.46 mm/sup 2/ and has a power consumption of 4.5 mW. The measurement results corroborate with simulation results and show that the CT-LPF can achieve a cutoff frequency of as low as 0.25 Hz. This demonstrates the feasibility of current steering technique in the design of filter for low-frequency application.     

A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBTtechnology

We report a 72.8-GHz fully static frequency divider in AlInAs/InGaAs HBT IC technology. The CML divider operates with a 350-mV logic swing at less than 0-dBm input power up to a maximum clock rate of 63 GHz and requires 8.6 dBm of input power at the maximum clock rate of 72.8 GHz. Power dissipation per flip-flop is 55 mW with a 3.1-V power supply. To our knowledge, this is the highest frequency of operation for a static divider in any technology. The power-delay product of 94 fJ/gate is the lowest power-delay product for a circuit operating above 50 GHz in any technology. A low-power divider on the same substrate operates at 36 GHz with 6.9 mW of dissipated power per flip-flop with a 3.1-V supply. The power delay of 24 fJ/gate is, to our knowledge, the lowest power-delay product for a static divider operating above 30 GHz in any technology. We briefly review the requirements for benchmarking a logic family and examine the historical trend of maximum clock rate in high-speed circuit technology     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

A Pipelined 330-MHz Multiplier

An 8X8-bit multiplier test circuit developed in a 1-/spl mu/m NMOS technology is described. To achieve a high throughput rate, extensive pipelining is used in a semi-systolic fashion. It is shown that this saves area and allows for shorter cycle times compared to a pure systolic array. Problems with widely distributed lines (broadcasting) are avoided by a novel carry-save-adder cell. The data inputs and outputs are ECL compatible. The circuit contains 5480 MOSFET's in an active area of 0.6 mm/sup 2/. Effective channel lengths of 0.9 and 1.1 /spl mu/m are utilized for the enhancement and depletion transistors with a gate oxide thickness of 12.5 nm. The power dissipation is 1.5 W at a supply voltage of 3 V. The test chip operates up to a clock frequency of 330 MHz at room temperature and up to 600 MHz with liquid nitrogen cooling. This demonstrates the applicability of large-scale integrated MOS circuits in a frequency range of several hundred megahertz.     

Current-mode analogue integrated circuit for sliding-mode controlof switching power converters

An analogue integrated circuit designed to implement sliding-mode control laws for high frequency switching DC-DC power converters is presented. The circuit operates in current-mode, providing high speed, modularity and the capability of including compensating dynamics. Experimental results for a 0.8 μm complementary metal-oxide-semiconductor (CMOS) technology prototype validate the high-speed functionality of the proposed sliding-mode controller implementation     

A 32-bit execution unit in an advanced NMOS technology

The circuit and design of an experimental 32-bit execution unit are described. It is fabricated in a scaled NMOS single-layer poly-technology with 2-/spl mu/m minimum gate length and low-ohmic polycide for gates and interconnections. The chip (25000 transistors, 16 mm/SUP 2/, 61 pins) is designed with a high degree of regularity and modularity. The circuit performs logic and arithmetic operations and has an on-chip control ROM for instruction decoding. It operates with a single 5-V supply voltage. Measurements resulted in a typical power dissipation of 750 mW and a maximum operation frequency of 6.5 MHz. At this frequency a 32/spl times/32 bit multiplication is performed in less than 5.5 /spl mu/s.     

An ultralow-power UHF transceiver integrated in a standard digitalCMOS process: transmitter

In the first part of the paper, also in this issue of the JOURNAL, the design of the frequency synthesizer and receiver section of an FSK transceiver was described. It operates in the 434-MHz ISM (Industrial, Scientific, Medical) band and is realized in a standard digital 0.5-μm CMOS process. This companion paper focuses on the realization of the transmitter section. It includes a power amplifier, an upconverter, and the circuit generating the baseband quadrature signals with a continuous phase modulation. The overall measured efficiency of the packaged circuit is higher than 38% for a 1.2-V supply and an output power reaching 10 dBm at 433 MHz. The system is designed to still operate at 1-V supply, delivering more than 1 mW with an efficiency higher than 15%     

A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.     

A low local input 1.9 GHz Si-bipolar quadrature modulator with noadjustment

A 1.9 GHz quadrature modulator with an onchip 90° phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm×2.14 mm     

A 3-mW 1.0-GHz silicon-ECL dual-modulus prescaler IC

The authors present a 3-V dual-modulus (÷64/65, ÷128/129) prescaler that operates up to 1.0 GHz with a 3-mW (V_CC at 2.58 V) power consumption. Under the normal supply voltage of 3 V, the maximum operating frequency and power dissipation are 1.18 GHz and 5 mW, respectively. This has been achieved by accurate circuit simulation and by the use of a 0.2-μm bipolar technology     

A Novel Low Power Architecture for DLL-Based Frequency Synthesizers

This paper presents a novel DLL-based frequency synthesizer architecture to generate fractional multiples of reference frequency and reduce the power consumption of the frequency synthesis block. The architecture is adopted for French VHF application as an example. The DLL architecture allows for minimal area, while consuming low power. The proposed circuit can operate at a substantially low supply voltage. The circuit level and system level designs are presented. It was shown that for the mentioned standard, a mere 27 delay stages for VCDL are sufficient to cover French VHF band. Simulation results confirm the analytical predictions. The proposed DLL-based frequency synthesizer is implemented in a 0.13 μm CMOS technology. This fractional DLL-based frequency synthesizer is adopted for 176 MHz to 216 MHz with maximum power consumption of 2.62 mW and RMS jitter of 10 ps @ 216 MHz.     

2-GHz/2-mW and 12-GHz/30-mW dual-modulus prescalers in siliconbipolar technology

Two dual-modulus prescalers manufactured in a low-cost silicon bipolar technology are presented. The first circuit is optimized for low power consumption and operates up to 2 GHz at a power consumption of 2 mW. The second prescaler is optimized for high speed and operates up to 12 GHz with a power consumption of 30 mW. The prescalers have selectable divide ratios of 128/129 and 256/257, respectively     

CMOS analog front end of a transceiver with digital echocancellation for ISDN

A CMOS analog front-end which contains a novel pulse-shaping circuit, an extremely linear-line-driver state, an oversampling second-order noise-shaping coder, and a wake-up signal detector is discussed. An analog front-end for 4B 3T coded signals is realized in a 2.5-μm CMOS technology and operates up to 4.5 km with 0.4-mm-diameter lines, needing only one 5-V power supply. It is possible to transmit 2B 1Q coded signals also, using a modified pulse-shaping circuit     

关于变频液压调速系统的发展及应用综述

分析了传统的节流调速液压回路的不足之处，并介绍了变频液压技术的特点，指出了变频液压动力系统是一种从源头考虑功率匹配的全局型节能动力系统，它具有节能效果好、可简化液压回路、调速范围大、噪声小等优点。综述了国内外变频液压技术的发展过程、应用领域及研究现状。讨论了变频液压存在的问题，包括低速稳定性，响应的快速性．启动或换向时的平稳性，调速精度和效率等，并针对这些问题提出了多种不同的对策，最后对变频液压的发展作了展望。