基于ELEA-V的LVDS驱动器的老炼技术研究与应用

本文介绍了LVDS驱动器以及它的老炼方法,结合杭州可靠性仪器厂的老炼系统ELEA-V,以器件DS90LV032ATMC为例,分别提出了以数字信号为主和模拟信号为主的两种种老炼方案设计并验证,取得了一定的效果,对后期该类器件的老炼具有一定的借鉴作用。     

VXI总线四通道LVDS数据传输模块设计

针对国内测试系统开发中出现的低电压差分信号(LVDS)技术需求提出了一种VXI总线四通道LVDS数据传输模块的设计实现方法;以FPGA作为控制核心,利用Verilog HDL设计实现了VXI接口和HDLC通讯协议设计,并通过基于VXI总线的块传输方式和乒乓存储技术,完成了大批量数据的接收;另外,为确保LVDS信号的完整性,结合实际设计和调试经验,文中还分析了LVDS接口信号印制板布线和布局问题;该模块已用于测试系统开发,并实现了测试系统与被测设备的视频信号传输;应用结果表明,模块传输速度为4Mbit/s时误码率小于10-6。     

LVDS技术研究

随着现代科技的发展，信息交换量的增加，宽带高速传输成为迫切的需求，而传统的I／O标准已很难满足实际应用的需要，在这种情况下，LVDS（低电压差分信号）应而运生。本文主要阐述了LVDS的标准，特点，应用趋势及在实际应用中应注意的问题。     

新型低压低功耗LVDS高速驱动电路设计

本文提出了一种可工作在1.8V电压下的新型低压低功耗LVDS高速驱动模型及其电路设计,通过预加重、合并开关电流源并使其工作在亚阈值区域,该LVDS驱动电路的传输速率可达1.5Gb/s,其功耗为9.78 mW,这使得该电路能满足日益增长的低压低功耗应用需求.     

基于CPCI总线和LVDS的高速数据传输系统的设计

为了实时准确地接收处理大容量的高速数据,在深入研究CPCI总线的基础上,提出了一种基于CPCI总线和LVDS的高速数据传输系统的实现方法。以PCI9054为桥接器件,FPGA为微控制器,设计了将PCI Target单周期模式读写指令和DMA突发模式传输数据相结合的传输模式,在保证数据可靠传输的同时,提高了数据的传输速度。经实践测试,该设计工作稳定,传输准确,成功地完成了预期传输任务。     

基于PCI-E总线接口高速数据传输系统的关键电路研究设计

对PCI总线技术进行了改进,改进后的PCI-E除具有原有总线技术的特点外还具有一些新的特点:串行差分接口;传输速率达到了2.5 GT/s;具有多种传输模式;高级RAS,支持热插拔。PCI和PCI Express相比保留了PCI的Load-Store架构技术等。PCI Express采用串行的机制,PCI-Express较之PCI也更加灵活,比如支持多种传输速率;PCIExpress支持更多更先进的技术,比如支持RAS和热插拔。此外,它还有个很大的优点,与PCI软件100%兼容。     

LVDS技术及其在多信道高速数据传输中的应用

介绍LVDS技术及其在雷达系统中的应用,应用LVDS技术解决雷达系统中多信道、高速数据的传输问题。     

"VXI总线测试平台”仪器驱动器设计与实现

提出了一种设计VXI总线仪器驱动器的通用环境VIDDE的方法。该环境以Microsoft Windows为操作平台,利用VisualC 及Microsoft Access 为主要编程工具,完成了仪器驱动器操作接口、编程接口和I／O接口的生成,对实现自主版权的VXI软件测试平台具有重要参考价值。     

基于FPGA的BLVDS高速通信总线设计

测试总线是测试系统中的一个重要环节,是准确传输信号的关键。详细介绍了LVDS与BLVDS技术,在此基础上论述了BLVDS总线布置设计、PCB布线设计、数据格式设计及通信背板设计,并提出了一种基于FPGA的BLVDS总线设计,采用Verilog HDL实现FPGA内部逻辑电路设计,FPGA完成BLVDS总线上数据的接收、发送,以及数据的缓存。实验结果表明,该总线通信速度快、稳定、可靠。     

大功率白光LED驱动电路的双环检测方法

基于CSMC0.5μm标准CMOS工艺,设计了一种带有双环检测的大功率LED恒流驱动芯片。仿真结果表明,芯片可在2MHz频率下工作,驱动电流最高可达1.5A,在24V电源电压时,电源效率可达95%。当电源电压在6V跳变±10%,驱动1W350mA的LED时,LED电流精度达0.02%。对比单环检测模式,该电路的LED驱动电流响应时间缩短了近2/3。此模式在保持高精度恒流和高效率的同时,有效地缩短了LED驱动电流的响应时间。     

A novel gate driver circuit for depletion‐mode a‐IGZO TFTs

In this paper, a novel gate driver circuit, which can achieve high reliability for depletion mode in a‐InGaZnO thin‐film transistors (TFTs), was proposed. To prevent the leakage current paths for Q node effectively, the new driving method was proposed by adopting the negative gate‐to‐source voltage (V_GS) value for pull‐down units. The results showed all the V_OUT voltage waveforms were maintained at VGH voltage despite depletion‐mode operation. The proposed circuit could also obtain stable V_OUT voltage when the threshold voltage for all TFTs was changed from ?6.5 to +11.5 V. Therefore, the circuit can achieve high reliability regardless of threshold voltage value for a‐IGZO TFTs. In addition, the output characteristics and total power consumption were shown for the alternating current (AC)–driven and direct current (DC)–driven methods based on 120‐Hz full‐HD graphics (1920 × 1080) display panel. The results showed that the AC‐driven method could achieve improved V_OUT characteristics compared with DC‐driven method since the leakage current path for Q node can be completely eliminated. Although power consumption of the AC‐driven method can be slightly increased compared with the DC‐driven method for enhancement mode, consumption can be lower when the operation has depletion‐mode characteristics by preventing a leakage current path for pull‐down units. Consequently, the proposed gate driver circuit can overcome the problems caused by the characteristics of a‐IGZO TFTs.     

Design of a low‐power‐consumption a‐IGZO TFT‐based Vcom driver circuit with long‐term reliability

Abstract— An amorphous‐InGaZnO (a‐IGZO) thin‐film transistor (TFT)‐based Vcom driver circuit that has long‐term reliability and can be integrated with the pixel array on a panel has been designed. Owing to the Vcom inversion, the power consumed by the proposed driving scheme is 40% less than that consumed by the conventional line‐inversion method. The high mobility (>10 cm²/V‐sec) of the a‐IGZO TFTs allows the integration of devices with small channel widths (<750 μm) and thus keeps the overall device size small, which is important for displays with narrow bezels. The lifetime of the Vcom driver is improved by AC driving (by clocking the n‐th and (n + 1)‐th frame with 20 and 0 V, respectively) of the buffer TFTs.     

Power reduction using adiabatic charge method for PDP driver circuit

Abstract— By applying an energy‐recovery method to their driver circuits, the circuit power consumption of plasma displays can be reduced. However, further power reduction is necessary for large‐sized higher‐resolution displays such as used for Super HDTV. The ideal adiabatic charge method has been proven to be able to minimize circuit resistive element power consumption to 81 % of the conventional energy‐recovery‐circuit resistive‐element loss. An experimental pseudo‐adiabatic charge circuit that reduces the power consumption to about 90% of a conventional circuit has been demonstrated. The power consumption caused by both the resistance loss and the discharge loss of the switching‐element parasitic capacitances was analyzed.     

超低功耗智能移动心电监测设备

移动智能传感是健康监测与管理的关键技术.面向智能心电传感器技术领域,设计了传感、信号处理、通信三个低功耗模块,并从系统设计上协调配合以降低功耗,研发了微负荷和可长期监测的贴片式心电监测设备,并具备实时心电处理和心率检测功能.该智能传感设备体积为24 mm×16 mm×10 mm,质量为1.73g.采用80 mAh容量的锂聚合电池供电,在256 Hz采样率时可持续工作7天以上.数据无线上传至电脑后,上位机软件可进行心电图(ECG)实时显示、处理.此外,该设备亦可通过蓝牙将心率数据传输至手机,可持续工作14天以上.     

High‐reliability gate driver circuit to prevent ripple voltage

In this paper, a high‐reliability gate driver circuit is proposed to prevent multiple outputs. The proposed circuit ensures reliability of the pull‐up thin‐film transistor (TFT) by periodically discharging the Q node voltage to the low‐level voltage (VGL) in the off stage. In addition, the output node is composed of two pull‐down TFTs that are driven alternately to ensure stability against bias stress. Thus, because the reliabilities of the pull‐up and pull‐down TFTs can be guaranteed simultaneously, the stability of the entire circuit is improved. Based on the simulation results, the rising and falling times of the output pulse are stable within 1.77 and 1.28 μs, respectively, even when the threshold voltage of the entire TFT is shifted by +10.0 V. In addition, the ripple voltage of the proposed circuit is almost eliminated and is within 0.79% of the total swing voltage. Moreover, through current is prevented in the proposed circuit because the turn‐on durations of the pull‐up and pull‐down units are completely nonoverlapping, which suggests that unnecessary power consumption can be eliminated. Therefore, based on 2,160 stages, the total power consumption of the proposed circuit is reduced by 34.7 mW from 276.3 to 241.6 mW.     

基于ARM嵌入式系统的RFID驱动程序设计

针对RFID系统的应用需求,基于ARM9微处理器的S3C2440嵌入式系统,实现了nRF905无线收发器的数据传输,为RFID系统提供了底层软硬件接口.硬件使用基于S3C2440微控制器的嵌入式平台和单片无线收发器nRF905;软件使用ARM-Linux内核,利用上层应用程序发送接收数据,底层驱动程序进行硬件间的数据传...     

Current programming pixel circuit and data‐driver design for active‐matrix organic light‐emitting diodes

Abstract— We propose a new pixel design for active‐matrix organic light‐emitting diodes (AMOLEDs) employing five polycrystalline thin‐film transistors (poly‐Si TFTs) and one capacitor, which decreases the data current considerably in order to reduce the charging time compared with that of conventional current‐mirror structures. Also, the new pixel design compensates the threshold‐voltage degradation of OLEDs caused by continuous operation and the non‐uniformity of poly‐Si TFTs due to excimer‐laser annealing. The proposed pixel circuit was verified by SPICE simulation, based on measured TFT and OLED characteristics. We also propose current‐data‐driver circuitry that reduces the number of shift‐register signals for addressing the current data driver by one‐half.     

基于WinCE驱动程序的电源管理研究与设计

为了降低嵌入式终端系统的功耗、延长系统的待机时间和电池的使用寿命,设计了一种基于Windows CE操作系统的嵌入式终端背光驱动的电源管理系统;分析了WinCE下的流接口驱动程序模型和电源管理架构,研究了背光驱动程序的电源管理策略,包括设备电源状态和系统电源状态的变化以及IOCTL操作码的使用;最后,通过在注册表中设置指定时间的超时值,完成了显示设备的背光驱动的设计,合理的节省了移动设备的电能,满足了系统对背光的控制需求。