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1.
A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi 2 on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi 2 films were achieved on all narrow, long n + and p + poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi 2 films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n + and p + poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi 2 films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi 2 films 相似文献
2.
The authors report on the off-state gate current ( Ig ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant Ig at drain voltages as low as 4 V and an Ig injection efficiency reaching 0.8, as compared to 8.5 V and 10 -7 in SiO 2 devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that Ig in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure 相似文献
3.
N-channel metal oxide semiconductor field effect transistors (MOSFETs) using Ta 2O 5, gate oxide were fabricated. The Ta 2O 5 films were deposited by plasma enhanced chemical vapor deposition. The I DS-V DS and I DS-V GS characteristics mere measured. The electron mobility was 333 cm 2/V·s. The subthreshold swing was 73 mV/dec. The interface trapped charge density, the surface recombination velocity, and the minority carrier lifetime in the field-induced depletion region measured from gated diodes were 9.5×10 12 cm -2 eV -1, 780 cm/s and 3×10 -6 sec, respectively. A comparison with conventional MOSFETs using SiO 2 gate oxide was made 相似文献
4.
The switching properties of silicon structures comprising a p+- n junction and a metal electrode separated from the n-section of the p+- n junction by a semi-insulating (leaky) layer are presented. Two basic types of structure were studied: devices with relatively light doped n-sections, and those with relatively heavily doped sections. The switching voltage of the first group was found to be proportional to the product of the doping density, Nd and the square of the width of the n-section, and to be only very weakly temperature-dependent. The capacitance-voltage relationship of the device in the high-impedance mode was found to be of the form C−1 ∞ V1/2, and these measurements established that switching occurred just as the depletion region of the n-section under the gate electrode reached through to the p+-n junction. It was thus established that these devices were operating in the punch-through mode. In the second group of devices, the doping density of the n-section was increased by diffusing an n-well into the section. The switching properties were found to be quite different from the punch-through devices. The switching voltage was found to be independent of the width of the n-section and proportional to Nd−3/4. Capacitance measurements also showed that the depletion region in the n-section under the oxide at switching, varied with the doping concentration, and was substantially less than the width of the n-layer. It was thus concluded that switching in these devices was of the avalanche-mode type. 相似文献
5.
Boron ions ( 11B + of 3·7 to 7·4 × 10 11/cm 2 were implanted at 60–120 keV into the channel region of p-channel MNOS double layer insulated gate field effect transistors through 920–940 Å of SiO 2 and various thicknesses (300–1800 Å) of Si 3N 4 deposited on SiO 2. Subsequent annealing was performed in a nitrogen atmosphere at 1000°C for 30 min. Acceleration energy, implant dose and Si 3N 4 thickness dependences of the shift of the threshold voltage showed good agreement with the calculated results based on Ishiwara and Furukawa's theory for distribution of implanted atoms in the double layered substrate, using the projected ranges and standard deviations larger than LSS predictions by the factor of 1·2 for SiO 2 and 1·3 for Si 3N 4, respectively. The results on the gain terms and the breakdown voltages were qualitatively the same as those of 11B +-implanted p-channel MOS transistors. 相似文献
6.
High mobility polycrystalline Si thin-film transistors (poly-Si TFTs) are firstly fabricated on flexible stainless-steel substrates 100 μm thick through low-temperature processes where both active Si and gate SiO 2 films are deposited by glow-discharge sputtering and the Si films are crystallized by KrF excimer laser irradiation. The gate SiO 2 films are sputter-deposited in oxygen atmosphere from the SiO 2 target. Resulting poly-Si TFTs show excellent characteristics of mobility of 106 cm 2/V·s and drain current on-off ratio of as high as 1×10 6. Thus, the poly-Si TFTs are very promising for realizing novel flat panel displays of lightweight and rugged LCDs and LEDs 相似文献
7.
6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n + source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm 2 for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm 2 delivers a forward drain current of 0.3 A at Y GS=10 V and V DS=8 V. The specific on resistance was determined to 82 mΩdcm 2 at 50 mV drain source voltage and at V GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer 相似文献
8.
Metal-nitride-semiconductor FETs (MNSFETs) having channel lengths down to 100 mm and a novel jet vapor deposited (JVD) Si 3N 4 gate dielectric have been fabricated and characterized. When compared with MOSFETs having a thermal SiO 2 gate insulator, the MNSFETs show a comparable drain current drive, transconductance, subthreshold slope and pre-stress interface quality. A novel charge pumping technique is employed to characterize the hot-carrier induced interface-trap generation in MNSFETs and MOSFETs. Under identical substrate current during stress, MNSFETs show less interface-state generation and drain current degradation, for various channel lengths, stress times and supply voltages, despite the fact that the Si-Si 3N 4 barrier (2.1 eV) is lower than the Si-SiO 2 barrier (3.1 eV). The time and voltage dependence of hot-carrier degradation has been found to be distinctly different for MNSFETs compared to SiO 2 MOSFETs 相似文献
9.
We present a new ohmic contact material NiSi 2 to n-type 6H-SiC with a low specific contact resistance. NiSi 2 films are prepared by annealing the Ni and Si films separately deposited on (0 0 0 1)-oriented 6H-SiC substrates with carrier concentrations ( n) ranging from 5.8×10 16 to 2.5×10 19 cm −3. The deposited films are annealed at 900 °C for 10 min in a flow of Ar gas containing 5 vol.% H 2 gas. The specific contact resistance of NiSi 2 contact exponentially decreases with increasing carrier concentrations of substrates. NiSi 2 contacts formed on the substrates with n=2.5×10 19 cm −3 show a relatively low specific contact resistance with 3.6×10 −6 Ω cm 2. Schottky barrier height of NiSi 2 to n-type 6H-SiC is estimated to be 0.40±0.02 eV using a theoretical relationship for the carrier concentration dependence of the specific contact resistance. 相似文献
10.
Abstract-We report Al 2O 3Zln 0.53Ga 0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n + regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In 0.53Ga 0.47As channel with an In 0.4sAl 0.52As back confinement layer and the n ++ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I D = 0.95 mA/mum current density at V GS = 4.0 V and g m = 0.45 mS/mum peak transconductance at V DS = 2.0 V. 相似文献
11.
N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta 2O 5 gate dielectric were fabricated. An intrinsic Ta 2O 5/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta 2O 5/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage V DS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode 相似文献
12.
Device performances of MOSFETs with SiO 2-xF x gate oxides prepared by an extremely low-temperature (15°C) liquid phase deposition (LPD) method were investigated. The electrical characteristics, including threshold voltage of 2.1 V, peak effective mobility (μ eff) of 525 cm 2/V·s, and subthreshold swing of 134 mV/decade, show the devices exhibit comparable performance to other low-temperature processed MOSFETs. This demonstrates that LPD SiO 2-xF x can be a suitable candidate for future gate insulators in low-temperature processed MOSFETs 相似文献
13.
The authors study the degradation of MOSFET current-voltage (V-I) characteristics as a function of polysilicon gate concentration (N p ), oxide thickness (t ox) and substrate impurity concentration (N D) using measured and modeled results. Experimentally it is found that for MOSFETs with thin gate oxide (t ox≈70 Å) and high substrate concentration (N D ≈1.6×10 17 cm -3) the reduction in the drain current I DS can be as large as 10% to 20% for devices with insufficiently doped polysilicon gate (5×10 18 ⩽N p⩽1.6×10 19 cm -3). Theoretically it is shown that the drain current degradation becomes more pronounced as N p decreases, t ox decreases, or N D, increases. A modified Pao-Sah model that takes into account the polysilicon depletion effect and an accurate gate-field-dependent mobility model are used to compute I-V characteristics for various values of N p, t ox, and N D. Good agreement between experimental and modeled results is observed over a wide range of devices 相似文献
14.
Ultra thin high- k zirconium oxide (equivalent oxide thickness 1.57 nm) films have been deposited on strained-Si/relaxed-Si 0.8Ge 0.2 heterolayers using zirconium tetra- tert-butoxide (ZTB) as an organometallic source at low temperature (<200 °C) by plasma enhanced chemical vapour deposition (PECVD) technique in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. The trapping/detrapping behavior of charge carriers in ultra thin ZrO 2 gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO 2 is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO 2 layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10 −19 cm 2 as compared to 10 −16 cm 2 in SiO 2 has been observed. The trapping charge density, Qot and charge centroid, Xt are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, tbd > 1500 s) is observed under high constant voltage stress. 相似文献
15.
Deposition and electrical properties of high dielectric constant (high- k) ultrathin ZrO 2 films on tensilely strained silicon (strained-Si) substrate are reported. ZrO 2 thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage ( C– V), current–voltage ( I– V), and conductance–voltage ( G– V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO 2 thin films as an alternative as gate dielectrics. Compatibility of ZrO 2 as a gate dielectric on strained-Si is shown. 相似文献
16.
The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN 2 temperatures on n-channel FETs for both ONO and conventional SiO 2 films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO 2 devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel 相似文献
17.
An organic thin-film transistor (OTFTs) having OTS/SiO 2 bilayer gate insulator and MoO 3/Al electrode configuration between gate insulator and source–drain (S–D) electrodes has been investigated. Thermally grown SiO 2 layer is used as the OTFT gate dielectric and copper phthalocyanine (CuPc) for an active layer. We have found that using silane coupling agents, octadecyltrichlorosilane (OTS) on SiO 2, surface energy of SiO 2 gate dielectric is reduced; consequently, the device performance has been improved significantly. This OTS/SiO 2 bilayer gate insulator configuration increases the field-effect mobility, reduces the threshold voltage and improves the on/off ratios simultaneously. The device with MoO 3/Al electrode has similar source–drain current ( IDS) compared to the device with Au electrode at same gate voltage. Our results indicate that using double-layer of insulator and modified electrode is an effective way to improve OTFT performance. 相似文献
18.
This work investigated the channel layer of polycrystalline silicon (poly-Si) thin film transistors (TFTs) prepared by amorphous silicon (a-Si) films deposited using Si 2H 6 gas. The recrystallization of channel layers, source/drain, gate electrodes and post implant anneal were performed at the same time. Due to the larger grain size, the device has higher field effect mobility than SiH 4 deposited devices. These devices were also subsequently passivated by NH 3 plasma. The NH 3 plasma significantly improves the n-channel devices; however, the improvement of p-channel devices is limited. Especially, the threshold voltage of n-channel devices is significantly shifted toward the negative gate voltage than the shift magnitude of p-channel devices. To investigate the band gap width and Fermi level by determining the leakage activation energy, it is found that the channel film is changed slightly from p-type to n-type. These results may be attributed to the donor effect by NH 3 plasma passivation. 相似文献
19.
We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ e is not degraded at channel dopant density N a lower than 1×10 17 cm -3, according to an experimental universal relationship between υ e and the low field mobility. On the other hand, there is a most suitable N a condition for suppression of statistical threshold voltage fluctuations. This most suitable N a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 17 cm -3 in both cases. Therefore, this most suitable N a condition is consistent with the above N a condition for carrier velocity. Consequently, new N a conditions for nano region devices are introduced in this study. N a should be designed to be of the order of 1×10 16 cm -3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively 相似文献
20.
A self-assembly patterning method for generation of epitaxial CoSi 2 nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n +-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO 2 and 300 nm Si 3N 4. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi 2 layer and a subsequent out-diffusion process to form the n +-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated. 相似文献
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