质子引入的6T SRAM单粒子翻转截面预测模型

提出了一种基于SOI工艺6T SRAM单元质子辐射的单粒子饱和翻转截面的预测模型,该模型通过器件物理来模拟辐照效应,利用版图和工艺参数来预测质子引入的单粒子饱和翻转截面。该模型采用重离子的SPICE测试程序对质子辐射的翻转截面进行预测,该方法简单高效,测试实例表明在0.15μm SOI工艺下,预测的质子引入的单粒子翻转饱和截面和实际测试的翻转截面一致。     

基于入射距离的一维瞬态电流源注入模型研究

在深亚微米工艺下,单粒子效应引入的瞬态电流与粒子入射位置有关。基于粒子入射距离,提出了一种针对电路级仿真的一维瞬态电流源注入模型。结果显示,电流源模型与三维TCAD仿真得到的瞬态电流形状拟合更好,NMOS和PMOS器件收集电荷量的计算误差分别下降了66.9%和65.0%。提出的电流源模型能够精确地反映粒子入射位置改变时6T SRAM电路的翻转情况,能更好地用于大规模集成电路的单粒子效应电路级模拟分析。     

部分耗尽PD CMOS/SOI器件SEU模型分析

通过计算机模拟分析CMOS/SOI器件中单粒子效应的影响,采用二维模拟软件MEDICE,建立了器件发生单粒子效应时内部电荷的分布模型.利用电荷分布模型建立了CMOS/SOI器件在入射不同LET值时的离子与器件中瞬态电流的关系曲线;并建立了离子入射点的不同位置与瞬态电流的关系曲线.从理论上提供了一种分析器件SEU的手段.     

14 nm SOI FinFET器件单粒子瞬态的复合双指数电流源模型

单粒子瞬态(SET)的电路仿真通常是注入双指数电流源来模拟,然而,纳米FinFET器件的SET采用单个双指数电流源模拟会带来较大误差。TCAD仿真结果较准确,但耗时较长,为了较为准确地电路仿真SET,提出了一种SET的复合双指数电流源模型。利用TCAD对电学特性校准的14 nm SOI FinFET器件的SET进行仿真,通过分析瞬态电流波形,对比双指数模型特点,提取特征参数,并利用遗传算法对模型参数进行优化处理,得到了关于线性能量转移(LET)的复合双电流源参数的解析模型。利用此复合双指数电流源模型与TCAD得到的瞬态电流波形、峰值和收集电荷量进行对比检验。结果显示,本文模型得到的SET电流波形与TCAD的基本吻合,与TCAD相比,模型的峰值电流的平均误差和最大误差分别为3.00%、5.06%;收集电荷量的平均误差和最大误差分别为4.02%、7.17%。     

0.5μm部分耗尽SOI MOSFET中的寄生双极效应

0.5μm部分耗尽SOI MOSFET的寄生双极效应严重影响了SOI器件和电路的抗单粒子和抗瞬态γ辐射能力。文中显示,影响0.5μm部分耗尽SOI NMOSFET寄生的双极器件特性的因素很多,包括NMOSFET的栅上电压、漏端电压和体接触等,尤其以体接触最为关键。在器件处于浮体状态时,0.5μm SOI NMOSFET的寄生双极器件很容易被触发,导致单管闭锁。因此,在设计抗辐射SOI电路时,需要尽量降低SOI NMOSFET寄生双极效应,以提高电路的抗单粒子和抗瞬态γ辐射能力。     

SOI CMOS SRAM单元单粒子翻转效应的模拟

为简单快速模拟静态随机存储器(SRAM)的单粒子效应,在二维器件数值模拟的基础上,以经典的双指数模型为原型,通过数值拟合得到了单粒子效应瞬态电流脉冲的表达式,考虑晶体管偏压对瞬态电流的影响,得到修正的瞬态电流表达式,将其带入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟,通过与实际单粒子实验结果的对比,验证了这种模拟方法的实用性。     

0.13μm全耗尽绝缘体上硅晶体管单粒子效应仿真研究

利用计算机辅助设计Silvaco TCAD仿真工具,研究了0.13μm全耗尽绝缘体上硅(FD-SOI)晶体管单粒子瞬态效应,分析了不同线性能量转移(LET)、单粒子入射位置和工作偏置状态对单粒子瞬态的影响。结果表明,LET值的增加会影响沟道电流宽度,加大单粒子瞬态峰值及脉冲宽度。受入射位置的影响,由于栅极中央收集的电荷最多,FD-SOI器件的栅极中央附近区域单粒子瞬态效应最敏感。单粒子瞬态与器件工作偏置状态有很强的相关性,器件处于不同工作偏置状态下,关态偏置受单粒子效应影响最大,开态偏置具有最小的瞬态电流峰值和脉宽。     

基于25 nm FinFET结构的SRAM单粒子效应研究

对基于25 nm FinFET结构的SRAM单粒子效应进行研究。使用Synopsys Sentaurus TCAD仿真软件进行器件工艺校准,并对独立3D FinFET器件以及包含FinFET器件和HSpice模型的混合电路(如6管SRAM单元)进行单粒子瞬态仿真。通过改变重粒子入射条件,分析影响瞬态电流峰值、脉宽、漏极翻转阈值等参数的因素。研究发现,混合模型中,FinFET结构器件的漏极翻转阈值为0.023 MeV·cm²/mg,对未来基于FinFET结构的器件及电路结构的加固提出了更高的要求。     

粒子入射条件对28nm SRAM单元单粒子电荷共享效应影响的TCAD仿真研究

利用器件仿真工具TCAD,建立28 nm体硅工艺器件的三维模型,研究了粒子入射条件和器件间距等因素对28 nm体硅工艺器件单粒子效应电荷共享的影响规律。结果表明,粒子LET值增大、入射角度的增大、器件间距的减小和浅槽隔离(STI)深度的减少都会增加相邻器件的电荷收集,增强电荷共享效应,影响器件敏感节点产生的瞬态电流大小;SRAM单元内不同敏感节点的翻转阈值不同,粒子LET值和入射角度的改变会对SRAM单元的单粒子翻转造成影响;LET值和粒子入射位置变化时,多个SRAM单元发生的单粒子多位翻转的位数和位置也会变化。     

簿全耗尽SOI膜N沟道MOSFET强反型电流模型

本文在仔细分析薄膜SOI器件特点及其特殊物理效应的基础上,发展了电路模拟所需要的N沟道薄全耗尽SOI膜MOSFET强反型电流模型.模拟计算和实际SOI器件测试结果之间的对比证实,在合理提取器件参数的情况下,该模型公式可较好地描述薄膜SOI器件的电流特性.     

Diode forward and reverse recovery model for power electronic SPICEsimulations

A pn-diode micro-model representing forward and reverse recovery phenomena for power electronic simulation, especially simulations using SPICE2 is presented. The model is proposed to compensate the incompleteness of the diode model in current circuit simulation packages. In the forward recovery submodel, the diode bulk resistance modulation and its forward current dependence are included. In the reverse recovery submodel, the charge control equation for excess storage carriers is employed to simulate the detailed behavior. A procedure is described for extracting the model's physical parameters from data sheet information. The model is verified by a comparison of experimental results for several different tests with SPICE simulations. A discussion is given of extending the applicability of the micro-model to the simulation of p-i-n diode behaviour     

Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop

A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy. Post-processing of the data from the laser mapping facilitated the plotting of the cross-section versus laser energy curve. We found a clear shift in the cross-section curves after voltage stress of 130 h. Comparisons of data revealed at least a doubled increase in sensitive areas after voltage stress. During the voltage stress, various electrical parameters were monitored and changes were observed. It was found that the increase in SEU sensitivity is related to electrical parameter changes and SPICE simulation results concur likewise.     

An accurate charge control approach for modeling excess phase shiftin the base region of bipolar transistors

The conventional charge control approach is extended to enable the accurate determination of excess phase shift in the ac common-emitter current gain of bipolar transistors arising from distributed stored minority carrier charge in the neutral base. Generalized expressions, valid for transistors with arbitrary impurity profiles and position-dependent transport parameters, are presented from which the excess phase shift can be determined solely from device structure and process data. The ac model parameters which result from the extended charge control approach are used in an existing high-frequency compact nonquasi-static bipolar model which is suitable for SPICE simulation     

Physical modeling of the power VDMOST for computer-aided design ofintegrated circuit

This paper presents a methodology for physical modeling of the vertical double-diffused MOS transistor (VDMOST) for power-integrated-circuit (PIC) design. The circuit model comprises the regional models derived from basic semiconductor equations. The unique features of the VDMOST such as quasi-saturation, nonlinear inter-electrode capacitances, reverse-recovery current, and temperature dependencies are accurately modeled based on device simulations. The composite model is implemented in Saber and SPICE2G.6 source code. It is verified against steady-state and capacitance-voltage measurements on test devices. A parameter extraction routine is developed, and a system that links ICCAP and Saber is set up that performs measurement, simulation, and parameter extraction. The application of the described model in computer-aided design (CAD) is demonstrated for several power-electronic circuits     

基于器件仿真的参数提取方法研究

介绍器件参数提取的意义,并对基于工艺的参数提取和基于器件仿真的参数提取两种方法进行了比较。根据0.35 μm SOI CMOS工艺参数,构造出部分耗尽SOI NMOS结构。基于BSIM SOI模型采用局部优化,单器件提取的策略进行参数提取。最后通过将仿真与实际测试得到的参数比较,验证了该方法的准确性。     

Parameterized SPICE model for a phase-change RAM device

A simple form of a SPICE macro model for a generic phase-change random access memory device is presented. The approach is based upon lumped parameter multiple level models. The SPICE implementation is described using a series of increasingly complex modeling blocks for dc to transient analysis. The effect of nonlinear phase switching during the programming cycle is demonstrated in a SPICE simulation and compared to experimental data.     

An automatic gain control circuit with TiO2 memristor variable gain amplifier

An automatic gain control (AGC) topology with a variable gain amplifier utilizing a titanium dioxide (TiO₂) memristor is described. A system analysis technique is developed based on the published physical charge-controlled memristor models and unique properties of this passive device. A linearized feedback loop amplitude model is used to design the AGC, and a design tradeoff analysis based on distortion performance is developed. The analysis results are verified with SPICE simulation including a TiO₂ memristor SPICE model.     

基于主方程单电子晶体管模拟新方法

在对单电子晶体管主方程模型及主方程的解法详细的分析的基础上,把单电子晶体管主方程模型和SP ICE的ABM功能结合,提出了基于主方程的单电子晶体管SP ICE模型。该模型由一个非线性电压控制电流源、非线性电压控制电压源、电容构成。并利用该模型对单电子晶体管V-I特性进行SP ICE模拟,同直接解主方程解法相比,仿真结果表明该模型具有合理的精确度。     

一种新型隧穿场效应晶体管

提出了一种新型隧穿场效应晶体管(TFET)结构,该结构通过在常规TFET靠近器件栅氧化层一侧的漏-体结界面引入一薄层二氧化硅(隔离区),从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿(BTBT),减弱TFET的双极效应,实现大幅度降低器件泄漏电流的目的。利用TCAD仿真工具对基于部分耗尽绝缘体上硅(PDSOI)和全耗尽绝缘体上硅(FDSOI)的TFET和新型TFET结构进行了仿真与对比。仿真结果表明,当隔离区宽度为2 nm,高度大于10 nm时,可阻断PDSOI TFET的BTBT,其泄漏电流下降了4个数量级;而基于FDSOI的TFET无法彻底消除BTBT和双极效应,其泄漏电流下降了2个数量级。因此新型结构更适合于PDSOI TFET。