Built-in ESD Protection for RFID Tag ICs

The built-in Electro-Static discharge (ESD) protection circuits for Radio frequency identification (RFID) tag ICs are proposed.The ESD protection function is built into the rectifier and amplitude limiter.The rectifier and limiter are connected directly to the RF interface,and some transistors can discharge the larger current.These transistors can be used to build ESD protection circuits,through the redesign and optimization.The built-in ESD protection circuits can improve the ESD protection level and reduce the layout area.The circuits have been fabricated in 0.18μm CMOS process.The test results show that the built-in ESD protection circuits work well under 4kV ESD pressure and save as much as 72％ of the layout area compare with foundry standard ESD protection cells.     

抗辐射加固版图技术的性能比较

Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOl device and their corresponding advantages and disadvantages are studied in detail. Under 0.13μm bulk silicon and SOl process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout （protection ring for bulk silicon DFF, T-gate for SO! DFF）, while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design.     

A novel double-trench LVTSCR used in the ESD protection of a RFIC

A low-voltage triggering silicon-controlled rectifier(LVTSCR),for its high efficiency and low parasitic parameters,has many advantages in ESD protection,especially in ultra-deep sub-micron(UDSM) IC and high frequency applications.In this paper,the impact factors of the snapback characteristics of a LVTSCR and the configuring modes are analyzed and evaluated in detail.These parameters include anode series resistance,gate voltage,structure and size of devices.In addition,a double-trench LVTSCR is presented that can increase the hold-on voltage effectively and offers easy adjustment.Also,its snapback characteristics can obey the ESD design window rule very well.The strategy of ESD protection in a RFIC using a LVTSCR is discussed at the end of the paper.     

A novel HBT trigger SCR in 0.35 μm SiGe BiCMOS technology

The silicon-controlled rectifier (SCR) device is known as an efficient electrostatic discharge (ESD) protection device due to the highest ESD robustness in the smallest layout area. However, SCR has some drawbacks, such as high trigger voltage and low holding voltage. In order to reduce the trigger voltage of the SCR device for ESD protection, a new heterojunction bipolar transistor (HBT) trigger silicon controlled rectifier (HTSCR) device in 0.35 μm SiGe BiCMOS technology are proposed. The underlying physical mechanisms critical to the trigger voltage are demonstrated based on transmission line pulsing (TLP) measurement and physics-based simulation results. The simulation results prove that the trigger voltage of the HTSCR is decided by the collector-to-emitter breakdown voltage of the HBT structure in floating base configuration. The ESD experiment test results demonstrate the HTSCR can offer superior performance with a small trigger voltage, an adjustable holding voltage and a high ESD robustness. In comparison to the conventional MLSCR, the trigger voltage of the fabricated HTSCR can reduce to less than 50% of that of the MLSCR, and the I_t2 of the HBT trigger SCR is 80% more than that of the MLSCR.     

Off-State Breakdown Characteristics of Body-Tied Partial-Depleted SOI nMOS Devices

Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology，respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.     

一种用于提高ESD保护器件开启速度的新型变化横向基区 掺杂结构双触发晶闸管

The turn-on speed of electrostatic discharge （ESD） protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device （DTSCR） can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p-n-p and n-p-n transistors. Using the variation lateral base doping （VLBD） structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure （VLBD_DTSCR） is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n-p-n and p--n-p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.     

Research on Electric Field Confinement Effect in Silicon LED Fabricated by Standard CMOS Technology

The wedge-shaped and leaf-type silicon light-emitting devices(LED)are designed and fabricated with the Singapore Chartered Semi Inc.’s dual-gate standard 0.35μm CMOS process.The basic structure of the two devices is N well-P+ junction.P+ area is the wedge-shaped structure,which is embedded in N well.The leaf-type silicon LED device is a combination of the three wedge-shaped LED devices.The main difference between the two devices is their different electrode distribution,which is mainly in order to analyze the application of electric field confinement(EFC).The devices’ micrographs were measured with the Olympus IC test microscope.The forward and reverse bias electrical characteristics of the devices were tested.Light measurements of the devices show that the electrode layout is very important when the electric field confinement is applied.     

InP HBT 在0.2GHz 至220 GHz频段稳定性研究

The frequency stabilities of InP DHBTs in a broadband over 1 to 220 GHz are investigated. A hybrid-topology small-signal model is used to accurately capture the parasitics of devices. The model parameters are extracted from measurements analytically. The investigation results show that the excellent agreement between the measured and simulated data is obtained in the frequency range 200 MHz to 220 GHz. The dominant parameters of the-topology model, bias conditions and emitter area have significant effects on the stability factor K. The HBT model can be unconditionally stable by reasonable selection of the proper bias condition and the physical layout of the device.     

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop (PLL)-based frequency synthesizer used in IEEE 1394b physical (PHY) system is presented in this paper. The PLL’s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL’s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 m complementary metal oxide semiconductor (CMOS) technology.     

一种基于保角变换的环形栅晶体管用作ESD防护器件的建模方法

This paper proposes a novel technique for modeling the electrostatic discharge （ESD） characteristic of the enclosed-gate layout transistors （ELTs）. The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELF is decomposed into edge and comer transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM （Berkeley Short- channel IGFET Model）. Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.     

5V CMOS中GGNMOS ESD失效电流和沟道长度正向关系的分析

Contrary to general understanding,a test result shows that devices with a shorter channel length have a degraded ESD performance in the advanced silicided CMOS process.Such a phenomenon in a gate-grounded NMOSFET(GGNMOS) was investigated,and the current spreading effect was verified as the predominant factor. Due to transmission line pulse(TLP) measurements and Sentaurus technology computer aided design(TCAD) 2-D numerical simulations,parameters such as current gain,on-resistance and power density were discussed in detail.     

Double-πfully scalable model for on-chip spiral inductors

A novel double-πequivalent circuit model for on-chip spiral inductors is presented.A hierarchical structure, similar to that of MOS models is introduced.This enables a strict partition of the geometry scaling in the global model and the model equations in the local model.The major parasitic effects,including the skin effect,the proximity effect,the inductive and capacitive loss in the substrate,and the distributed effect,are analytically calculated with geometric and process parameters in the local-level.As accurate values of the layout and process parameters are difficult to obtain,a set of model parameters is introduced to correct the errors caused by using these given inaccurate layout and process parameters at the local level.Scaling rules are defined to enable the formation of models that describe the behavior of the inductors of a variety of geometric dimensions.A series of asymmetric inductors with different geometries are fabricated on a standard 0.18-μm SiGe BiCMOS process with 100Ω/cm substrate resistivity to verify the proposed model.Excellent agreement has been obtained between the measured results and the proposed model over a wide frequency range.     

A NOVEL OVER—VOLTAGE PROTECTION METHOD FOR 600V SPIC

A novel over-voltage protection method for 600V BPIC(Smart Power IC) is proposed in this paper.The combining FFLRs(Floating Field Limiting Rings) system is designed to be a voltage detector.The detector‘s voltage can turn off the switch of the APFC(Active Power Factor Correction )Circuit and the bus voltage would fall from 600VDC to 300VDC,so the SPIC and power devices can be protected.The advantages of this design are that the total protection circuits are integrated in SPIC and technologically compatible with CMOS or BCD(Bipolar CMOS-DMOS) technology.     

Investigation of the polysilicon p-i-n diode and diode string as a process compatible and portable ESD protection device

正The polysilicon p-i-n diode displays noticeable process compatibility and portability in advanced technologies as an electrostatic-discharge(ESD) protection device.This paper presents the reverse breakdown,current leakage and capacitance characteristics of fabricated polysilicon p-i-n diodes.To evaluate the ESD robustness,the forward and reverse TLPⅠ-Ⅴcharacteristics were measured.The polysilicon p-i-n diode string was also investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. Finally,to explain the effects of the device parameters,we analyze and discuss the inherent properties of polysilicon p-i-n diodes.     

高压gg-LDMOS在ESD应力条件下的热特性研究

The thermal characteristics of high voltage gg-LDMOS under ESD stress conditions are investigated in detail based on the Sentaurus process and device simulators.The total heat and lattice temperature distributions along the Si–SiO2 interface under different stress conditions are presented and the physical mechanisms are discussed in detail.The influence of structure parameters on peak lattice temperature is also discussed,which is useful for designers to optimize the parameters of LDMSO for better ESD performance.     

Dark current generating mechanisms in short wavelength infrared photovoltaic detectors

The current-voltage characteristics and quantum efficiencies of double layer planar heterostructure photodiodes were investigated. Results are reported on devices with cutoff wavelengths of 1.8, 2.4, and 3.3 μm. For these respective devices, the dominant currents for temperatures >250,>200,>150K are diffusion currents limited by shallow Shockley-Hall-Read (SHR) processes. The remarkable result is that the electrical and optoelectronic properties of these devices of diverse cut-off wavelength can be explained by simple models using independently measured layer parameters such as the minority carrier lifetimes. For all three cases, the analysis suggests that the same shallow (SHR) centers located at 78% of the energy gap are causing the observed effects. These traps located in then-type base of the device are not influenced by the magnitude of n-type doping and this observation was used to significantly improve the performance of the devices and validate the predictive capability of the models used in the analysis. The shallow centers appear to be process induced rather than grown-in. This assertion is based on the observation that changes in the annealing process led to an order of magnitude improvement in the minority carrier lifetime.     

Scaling trends in energy recovery logic: an analytical approach

This paper presents an analytical model to study the scaling trends in energy recovery logic.The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage,device threshold voltage and gate oxide thickness.The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale.This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

激光定位深亚微米CMOS SRAM单粒子翻转敏感区

The pulsed laser facility for SEU sensitivity mapping is utilized to study the SEU sensitive regions of a 0.18/zm CMOS SRAM cell. Combined with the device layout micrograph, SEU sensitivity maps of the SRAM cell are obtained. TCAD simulation work is performed to examine the SEU sensitivity characteristics of the SRAM cell. The laser mapping experiment results are discussed and compared with the electron micrograph information of the SRAM cell and the TCAD simulation results. The results present that the test technique is reliable and of high mapping precision for the deep submicron technology device.     

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate

This paper investigated the DC and RF performance of the InP double heterojunction bipolar transistors (DHBTs) transferred to RF CMOS wafer substrate.The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger,of 0.8μm in width and 5μm in length,are changed unobviously,while the cut-off frequency and the maximum oscillation frequency are decreased from 220 to 171 GHz and from 204 to 154 GHz,respectively.In order to have a detailed insight on the degradation of the RF performance,small-signal models for the InP DHBT before and after substrate transferred are presented and comparably extracted.The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself.     

Characterization analysis of UDSM LVTSCR under TLP stress

The characteristics of a low-voltage triggering silicon-controlled rectifier(LVTSCR) under a transmission line pulse(TLP) and the characteristics of high frequency are analyzed.The research results show that the anode series resistance has a significant effect on the key points of the snapback curve.The device characteristics can fit the requirements of a electrostatic discharge(ESD) design window by adjusting the anode series resistance. Furthermore,the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR.A steep rising edge will cause the turn-on voltage to increase.The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance,and its accuracy calculation is very important to the ESD design of high frequency circuits.Our research results provide a theoretical basis for the design of an ultra-deep sub-micron(UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.